Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00	93.33	100.00	100.00	98.90	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	489517046	1907727	0	0
intr_enable_rd_A	489517046	4179	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489517046	1907727	0	0
T8	133324	452509	0	0
T9	364522	57098	0	0
T10	0	182160	0	0
T14	0	69927	0	0
T15	0	290701	0	0
T16	0	33302	0	0
T57	6882	0	0	0
T71	0	276437	0	0
T72	0	22412	0	0
T73	0	79822	0	0
T74	0	37596	0	0
T75	118422	0	0	0
T76	645438	0	0	0
T77	19758	0	0	0
T78	498983	0	0	0
T79	116122	0	0	0
T80	277291	0	0	0
T81	124768	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489517046	4179	0	0
T4	461548	10	0	0
T5	790347	0	0	0
T6	473579	0	0	0
T7	225643	0	0	0
T14	0	93	0	0
T15	0	486	0	0
T16	0	51	0	0
T17	100584	0	0	0
T18	6088	0	0	0
T19	338925	0	0	0
T23	11869	0	0	0
T24	391845	0	0	0
T26	805765	0	0	0
T82	0	22	0	0
T83	0	62	0	0
T84	0	16	0	0
T85	0	35	0	0
T86	0	13	0	0
T87	0	57	0	0