Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

43171179

1

T1

473574

T2

696

T3

34900

full_word

38221894

1

T1

424645

T2

2009

T3

41537

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	81392653	1			T1	898219		T2	2705		T3	76437
auto[TlIntgErrCmd]	116	1			T64	8		T65	8		T66	6
auto[TlIntgErrData]	148	1			T64	8		T65	7		T66	8
auto[TlIntgErrBoth]	156	1			T64	4		T65	15		T66	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

37779084

1

T1

440379

T2

824

T3

39273

auto[1]

43613989

1

T1

457840

T2

1881

T3

37164

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	19574349	1			T1	225390		T2	493		T3	19974
auto[TlIntgErrNone]	partial	auto[1]	23596437	1			T1	248184		T2	203		T3	14926
auto[TlIntgErrNone]	full_word	auto[0]	18204536	1			T1	214989		T2	331		T3	19299
auto[TlIntgErrNone]	full_word	auto[1]	20017331	1			T1	209656		T2	1678		T3	22238
auto[TlIntgErrCmd]	partial	auto[0]	41	1			T64	3		T65	2		T66	2
auto[TlIntgErrCmd]	partial	auto[1]	67	1			T64	5		T65	3		T66	4
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T65	1		T139	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T65	2		T133	1		T135	1
auto[TlIntgErrData]	partial	auto[0]	82	1			T64	4		T65	5		T66	6
auto[TlIntgErrData]	partial	auto[1]	57	1			T64	4		T65	2		T66	2
auto[TlIntgErrData]	full_word	auto[0]	3	1			T136	1		T135	1		T140	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T134	1		T137	1		T140	1
auto[TlIntgErrBoth]	partial	auto[0]	66	1			T64	1		T65	5		T66	3
auto[TlIntgErrBoth]	partial	auto[1]	80	1			T64	2		T65	8		T66	2
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T134	1		T141	1		T138	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T64	1		T65	2		T66	1