Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00	93.33	100.00	100.00	98.90	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	474316135	2226711	0	0
intr_enable_rd_A	474316135	3997	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474316135	2226711	0	0
T8	258284	59963	0	0
T9	0	137201	0	0
T10	0	44372	0	0
T14	0	118694	0	0
T15	0	150776	0	0
T22	0	60627	0	0
T67	0	31627	0	0
T68	0	52216	0	0
T69	0	53789	0	0
T70	0	890	0	0
T71	38707	0	0	0
T72	359694	0	0	0
T73	561607	0	0	0
T74	19159	0	0	0
T75	653357	0	0	0
T76	836	0	0	0
T77	595265	0	0	0
T78	74677	0	0	0
T79	109010	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474316135	3997	0	0
T14	0	91	0	0
T15	0	239	0	0
T42	0	14	0	0
T80	760392	66	0	0
T81	0	44	0	0
T82	0	10	0	0
T83	0	64	0	0
T84	0	109	0	0
T85	0	9	0	0
T86	0	41	0	0
T87	48506	0	0	0
T88	20809	0	0	0
T89	369103	0	0	0
T90	13445	0	0	0
T91	37888	0	0	0
T92	1497	0	0	0
T93	54845	0	0	0
T94	287396	0	0	0
T95	96025	0	0	0