Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

48929141

1

T1

52687

T2

850957

T3

72366

full_word

43148957

1

T1

42125

T2

760874

T3

58031

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	92077668	1			T1	94812		T2	161183		T3	130397
auto[TlIntgErrCmd]	127	1			T74	4		T75	4		T76	3
auto[TlIntgErrData]	144	1			T74	3		T75	4		T76	4
auto[TlIntgErrBoth]	159	1			T74	3		T75	2		T76	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

43257633

1

T1

47579

T2

783277

T3

65453

auto[1]

48820465

1

T1

47233

T2

828554

T3

64944

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	22387290	1			T1	23870		T2	392646		T3	32667
auto[TlIntgErrNone]	partial	auto[1]	26541456	1			T1	28817		T2	458311		T3	39699
auto[TlIntgErrNone]	full_word	auto[0]	20870155	1			T1	23709		T2	390631		T3	32786
auto[TlIntgErrNone]	full_word	auto[1]	22278767	1			T1	18416		T2	370243		T3	25245
auto[TlIntgErrCmd]	partial	auto[0]	52	1			T74	1		T75	3		T76	1
auto[TlIntgErrCmd]	partial	auto[1]	66	1			T74	3		T75	1		T76	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T128	1		T134	1		T135	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T129	1		T136	1		T131	1
auto[TlIntgErrData]	partial	auto[0]	63	1			T74	1		T76	1		T133	6
auto[TlIntgErrData]	partial	auto[1]	71	1			T74	2		T75	2		T76	3
auto[TlIntgErrData]	full_word	auto[0]	5	1			T75	2		T129	1		T131	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T136	1		T132	2		T137	1
auto[TlIntgErrBoth]	partial	auto[0]	62	1			T75	1		T133	1		T128	3
auto[TlIntgErrBoth]	partial	auto[1]	81	1			T74	3		T75	1		T76	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T76	1		T138	2		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	13	1			T133	1		T129	1		T136	1