Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00	93.33	100.00	100.00	98.90	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	448028284	2037866	0	0
intr_enable_rd_A	448028284	2332	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	448028284	2037866	0	0
T7	96658	0	0	0
T10	0	192043	0	0
T11	104550	40483	0	0
T12	0	79673	0	0
T13	0	322518	0	0
T15	0	171770	0	0
T17	0	23081	0	0
T18	0	156657	0	0
T26	0	100417	0	0
T27	0	98811	0	0
T65	1231	0	0	0
T66	833	0	0	0
T77	0	167103	0	0
T78	178459	0	0	0
T79	408224	0	0	0
T80	42653	0	0	0
T81	748511	0	0	0
T82	677511	0	0	0
T83	580057	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	448028284	2332	0	0
T2	147332	4	0	0
T3	137615	0	0	0
T4	121497	0	0	0
T5	195032	0	0	0
T6	557340	0	0	0
T9	102810	0	0	0
T17	0	19	0	0
T18	0	97	0	0
T19	1859	0	0	0
T20	98613	0	0	0
T21	94196	0	0	0
T25	954337	0	0	0
T84	0	20	0	0
T85	0	44	0	0
T86	0	13	0	0
T87	0	22	0	0
T88	0	52	0	0
T89	0	55	0	0
T90	0	12	0	0