Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 45108506 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 42791823 1 T1 31616 T2 15033 T3 9850



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 41771130 1 T1 21388 T2 17358 T3 9025
values[0x0] 21583279 1 T1 15088 T2 6870 T3 5094
values[0x1] 24545920 1 T1 15563 T2 7814 T3 5557



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 34679204 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 53221125 1 T1 35541 T2 18858 T3 12043



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 284863 1 T1 172 T4 126 T6 227
valid_sources[0x01] 330428 1 T1 238 T4 115 T6 226
valid_sources[0x02] 281954 1 T1 201 T4 114 T6 211
valid_sources[0x03] 288329 1 T1 164 T4 136 T6 187
valid_sources[0x04] 290730 1 T1 221 T4 119 T6 205
valid_sources[0x05] 293066 1 T1 260 T4 111 T6 196
valid_sources[0x06] 289303 1 T1 215 T4 111 T6 206
valid_sources[0x07] 291873 1 T1 183 T4 121 T6 189
valid_sources[0x08] 294459 1 T1 166 T4 112 T6 206
valid_sources[0x09] 758166 1 T1 184 T4 102 T6 192
valid_sources[0x0a] 331235 1 T1 174 T4 98 T6 184
valid_sources[0x0b] 292480 1 T1 167 T4 124 T6 244
valid_sources[0x0c] 323576 1 T1 156 T4 108 T6 182
valid_sources[0x0d] 421755 1 T1 214 T4 138 T6 188
valid_sources[0x0e] 289383 1 T1 161 T4 120 T6 189
valid_sources[0x0f] 286013 1 T1 220 T4 103 T6 182
valid_sources[0x10] 458771 1 T1 208 T4 124 T6 199
valid_sources[0x11] 282695 1 T1 198 T4 121 T6 228
valid_sources[0x12] 292818 1 T1 196 T4 120 T6 207
valid_sources[0x13] 310151 1 T1 208 T4 104 T6 184
valid_sources[0x14] 350133 1 T1 258 T4 89 T6 210
valid_sources[0x15] 286298 1 T1 157 T4 103 T6 209
valid_sources[0x16] 293855 1 T1 221 T4 112 T6 204
valid_sources[0x17] 277703 1 T1 234 T4 109 T6 194
valid_sources[0x18] 296138 1 T1 215 T4 115 T6 196
valid_sources[0x19] 279136 1 T1 231 T4 98 T6 205
valid_sources[0x1a] 537181 1 T1 195 T4 132 T6 217
valid_sources[0x1b] 288374 1 T1 229 T4 108 T6 203
valid_sources[0x1c] 431195 1 T1 233 T4 121 T6 188
valid_sources[0x1d] 293126 1 T1 196 T4 117 T6 206
valid_sources[0x1e] 279789 1 T1 186 T4 99 T6 218
valid_sources[0x1f] 382309 1 T1 247 T4 131 T6 195
valid_sources[0x20] 285826 1 T1 179 T4 124 T6 206
valid_sources[0x21] 299846 1 T1 191 T4 136 T6 182
valid_sources[0x22] 326108 1 T1 204 T4 124 T6 198
valid_sources[0x23] 408210 1 T1 219 T4 133 T6 216
valid_sources[0x24] 330283 1 T1 229 T4 98 T6 180
valid_sources[0x25] 288386 1 T1 178 T4 117 T6 219
valid_sources[0x26] 286023 1 T1 192 T4 110 T6 185
valid_sources[0x27] 342149 1 T1 196 T4 114 T6 184
valid_sources[0x28] 281052 1 T1 198 T4 98 T6 214
valid_sources[0x29] 418856 1 T1 151 T4 118 T6 203
valid_sources[0x2a] 354922 1 T1 204 T4 118 T6 199
valid_sources[0x2b] 798380 1 T1 210 T4 110 T6 183
valid_sources[0x2c] 280426 1 T1 203 T4 120 T6 215
valid_sources[0x2d] 279438 1 T1 178 T4 116 T6 220
valid_sources[0x2e] 285202 1 T1 206 T4 112 T6 208
valid_sources[0x2f] 281418 1 T1 220 T4 102 T6 205
valid_sources[0x30] 286012 1 T1 213 T4 99 T6 216
valid_sources[0x31] 503466 1 T1 211 T4 112 T6 229
valid_sources[0x32] 277985 1 T1 204 T4 120 T6 216
valid_sources[0x33] 275449 1 T1 201 T4 120 T6 189
valid_sources[0x34] 297167 1 T1 229 T4 106 T6 191
valid_sources[0x35] 285146 1 T1 186 T4 98 T6 235
valid_sources[0x36] 295091 1 T1 255 T4 115 T6 228
valid_sources[0x37] 332549 1 T1 177 T4 111 T6 204
valid_sources[0x38] 290739 1 T1 208 T4 109 T6 228
valid_sources[0x39] 286921 1 T1 202 T4 94 T6 180
valid_sources[0x3a] 372105 1 T1 183 T4 119 T6 211
valid_sources[0x3b] 277873 1 T1 211 T4 113 T6 218
valid_sources[0x3c] 281634 1 T1 145 T4 107 T6 192
valid_sources[0x3d] 274146 1 T1 186 T4 134 T6 196
valid_sources[0x3e] 276019 1 T1 254 T4 121 T6 204
valid_sources[0x3f] 284692 1 T1 193 T4 124 T6 206
valid_sources[0x40] 350317 1 T1 154 T4 124 T6 215
valid_sources[0x41] 283149 1 T1 222 T4 109 T6 226
valid_sources[0x42] 433709 1 T1 229 T4 99 T6 194
valid_sources[0x43] 292297 1 T1 232 T4 110 T6 199
valid_sources[0x44] 276127 1 T1 228 T4 125 T6 206
valid_sources[0x45] 342325 1 T1 188 T4 110 T6 216
valid_sources[0x46] 296052 1 T1 219 T4 99 T6 215
valid_sources[0x47] 299590 1 T1 206 T4 107 T6 210
valid_sources[0x48] 293245 1 T1 158 T4 97 T6 202
valid_sources[0x49] 296140 1 T1 219 T4 121 T6 232
valid_sources[0x4a] 282386 1 T1 229 T4 105 T6 198
valid_sources[0x4b] 277414 1 T1 219 T4 119 T6 215
valid_sources[0x4c] 286556 1 T1 218 T4 106 T6 191
valid_sources[0x4d] 280888 1 T1 248 T4 104 T6 170
valid_sources[0x4e] 285041 1 T1 203 T4 108 T6 218
valid_sources[0x4f] 284022 1 T1 153 T4 87 T6 201
valid_sources[0x50] 305781 1 T1 207 T4 110 T6 193
valid_sources[0x51] 308560 1 T1 183 T4 110 T6 195
valid_sources[0x52] 282794 1 T1 247 T4 117 T6 218
valid_sources[0x53] 359564 1 T1 188 T4 95 T6 191
valid_sources[0x54] 287342 1 T1 225 T4 118 T6 196
valid_sources[0x55] 294603 1 T1 203 T4 118 T6 198
valid_sources[0x56] 280118 1 T1 220 T4 104 T6 201
valid_sources[0x57] 298554 1 T1 187 T4 130 T6 188
valid_sources[0x58] 283707 1 T1 179 T4 103 T6 198
valid_sources[0x59] 327325 1 T1 224 T4 125 T6 236
valid_sources[0x5a] 315030 1 T1 252 T4 112 T6 199
valid_sources[0x5b] 351657 1 T1 145 T4 90 T6 215
valid_sources[0x5c] 283479 1 T1 191 T4 120 T6 206
valid_sources[0x5d] 430672 1 T1 202 T4 145 T6 224
valid_sources[0x5e] 281995 1 T1 165 T4 104 T6 195
valid_sources[0x5f] 286001 1 T1 216 T4 117 T6 198
valid_sources[0x60] 278218 1 T1 210 T4 115 T6 213
valid_sources[0x61] 278761 1 T1 180 T4 115 T6 201
valid_sources[0x62] 277060 1 T1 203 T4 96 T6 195
valid_sources[0x63] 292914 1 T1 153 T4 114 T6 190
valid_sources[0x64] 289088 1 T1 233 T4 94 T6 205
valid_sources[0x65] 286348 1 T1 164 T4 113 T6 219
valid_sources[0x66] 342901 1 T1 206 T4 107 T6 194
valid_sources[0x67] 381240 1 T1 203 T4 108 T6 222
valid_sources[0x68] 282563 1 T1 222 T4 94 T6 193
valid_sources[0x69] 283808 1 T1 203 T4 121 T6 190
valid_sources[0x6a] 287490 1 T1 201 T4 107 T6 196
valid_sources[0x6b] 273140 1 T1 227 T4 140 T6 203
valid_sources[0x6c] 380774 1 T1 230 T4 108 T6 212
valid_sources[0x6d] 596692 1 T1 203 T2 32042 T4 139
valid_sources[0x6e] 287466 1 T1 168 T4 115 T6 208
valid_sources[0x6f] 281207 1 T1 189 T4 125 T6 186
valid_sources[0x70] 282243 1 T1 202 T4 103 T6 207
valid_sources[0x71] 284282 1 T1 201 T4 89 T6 197
valid_sources[0x72] 281061 1 T1 242 T4 129 T6 202
valid_sources[0x73] 282871 1 T1 186 T4 111 T6 202
valid_sources[0x74] 286736 1 T1 255 T4 119 T6 172
valid_sources[0x75] 283319 1 T1 211 T4 119 T6 217
valid_sources[0x76] 283750 1 T1 247 T4 121 T6 184
valid_sources[0x77] 455568 1 T1 209 T4 104 T6 213
valid_sources[0x78] 420964 1 T1 192 T4 105 T6 179
valid_sources[0x79] 281589 1 T1 199 T4 128 T6 212
valid_sources[0x7a] 282756 1 T1 205 T4 131 T6 161
valid_sources[0x7b] 288014 1 T1 229 T4 126 T6 208
valid_sources[0x7c] 286532 1 T1 192 T4 88 T6 162
valid_sources[0x7d] 292334 1 T1 203 T4 110 T6 176
valid_sources[0x7e] 300184 1 T1 247 T4 122 T6 194
valid_sources[0x7f] 281403 1 T1 204 T4 108 T6 188
valid_sources[0x80] 335371 1 T1 201 T4 120 T6 188



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 20657151 1 T1 10451 T2 8497 T3 4500
values[0x0] all_enables biggest_size 11922704 1 T1 11071 T2 3541 T3 2883
values[0x1] all_enables biggest_size 10211968 1 T1 10094 T2 2995 T3 2467

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%