Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

49395053

1

T1

20423

T2

17009

T3

9826

full_word

43069831

1

T1

31616

T2

15033

T3

9850

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	92464484	1			T1	52039		T2	32042		T3	19676
auto[TlIntgErrCmd]	130	1			T65	4		T66	3		T67	7
auto[TlIntgErrData]	141	1			T65	3		T66	4		T67	14
auto[TlIntgErrBoth]	129	1			T65	3		T66	3		T67	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

43200606

1

T1

21388

T2

17358

T3

9025

auto[1]

49264278

1

T1

30651

T2

14684

T3

10651

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	22434649	1			T1	10937		T2	8861		T3	4525
auto[TlIntgErrNone]	partial	auto[1]	26960034	1			T1	9486		T2	8148		T3	5301
auto[TlIntgErrNone]	full_word	auto[0]	20765762	1			T1	10451		T2	8497		T3	4500
auto[TlIntgErrNone]	full_word	auto[1]	22304039	1			T1	21165		T2	6536		T3	5350
auto[TlIntgErrCmd]	partial	auto[0]	56	1			T65	2		T66	1		T67	2
auto[TlIntgErrCmd]	partial	auto[1]	67	1			T65	1		T66	2		T67	3
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T69	1		T124	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T65	1		T67	2		T125	1
auto[TlIntgErrData]	partial	auto[0]	68	1			T65	1		T66	3		T67	8
auto[TlIntgErrData]	partial	auto[1]	62	1			T65	2		T66	1		T67	5
auto[TlIntgErrData]	full_word	auto[0]	8	1			T69	1		T120	2		T121	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T67	1		T120	1		T126	1
auto[TlIntgErrBoth]	partial	auto[0]	55	1			T65	3		T66	2		T67	4
auto[TlIntgErrBoth]	partial	auto[1]	62	1			T66	1		T67	5		T123	6
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T119	1		T69	3		T126	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T69	1		T127	3		T128	1