Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00	93.33	100.00	100.00	98.90	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	496657536	2462273	0	0
intr_enable_rd_A	496657536	3123	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	496657536	2462273	0	0
T9	523656	84381	0	0
T10	0	232032	0	0
T11	0	93069	0	0
T15	0	307084	0	0
T16	0	98103	0	0
T22	0	368029	0	0
T23	0	130861	0	0
T70	0	147334	0	0
T71	0	82148	0	0
T72	0	165396	0	0
T73	114341	0	0	0
T74	207872	0	0	0
T75	642952	0	0	0
T76	47468	0	0	0
T77	460187	0	0	0
T78	337821	0	0	0
T79	129487	0	0	0
T80	977810	0	0	0
T81	130958	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	496657536	3123	0	0
T9	0	131	0	0
T15	0	87	0	0
T16	0	125	0	0
T21	676651	0	0	0
T24	19479	0	0	0
T28	483016	0	0	0
T29	494155	98	0	0
T51	17246	0	0	0
T56	572772	8	0	0
T68	203987	0	0	0
T82	0	46	0	0
T83	0	27	0	0
T84	0	50	0	0
T85	0	33	0	0
T86	0	28	0	0
T87	35558	0	0	0
T88	476967	0	0	0
T89	386234	0	0	0