Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 41622233 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 39891867 1 T1 120845 T2 24103 T3 71918



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 38734928 1 T1 137921 T2 20588 T3 81923
values[0x0] 20052464 1 T1 62279 T2 11127 T3 37447
values[0x1] 22726708 1 T1 74472 T2 11341 T3 43854



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 32002004 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 49512096 1 T1 156077 T2 31980 T3 92588



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 315883 1 T1 934 T2 138 T4 22
valid_sources[0x01] 261134 1 T1 1128 T2 178 T4 16
valid_sources[0x02] 238088 1 T1 1084 T2 155 T4 39
valid_sources[0x03] 265557 1 T1 1014 T2 195 T4 18
valid_sources[0x04] 240122 1 T1 1161 T2 147 T4 33
valid_sources[0x05] 241348 1 T1 1052 T2 147 T4 16
valid_sources[0x06] 243497 1 T1 1053 T2 126 T4 10
valid_sources[0x07] 426594 1 T1 1019 T2 117 T4 23
valid_sources[0x08] 239917 1 T1 1180 T2 201 T4 29
valid_sources[0x09] 248123 1 T1 956 T2 161 T4 28
valid_sources[0x0a] 526891 1 T1 1113 T2 167 T4 24
valid_sources[0x0b] 243931 1 T1 1105 T2 215 T4 15
valid_sources[0x0c] 242566 1 T1 1109 T2 151 T4 24
valid_sources[0x0d] 236543 1 T1 1073 T2 154 T4 20
valid_sources[0x0e] 244675 1 T1 1098 T2 99 T4 19
valid_sources[0x0f] 235970 1 T1 1124 T2 185 T4 25
valid_sources[0x10] 252222 1 T1 1004 T2 192 T4 36
valid_sources[0x11] 244403 1 T1 1163 T2 167 T4 32
valid_sources[0x12] 245324 1 T1 1062 T2 207 T4 30
valid_sources[0x13] 255892 1 T1 1112 T2 176 T4 14
valid_sources[0x14] 247405 1 T1 1066 T2 219 T4 16
valid_sources[0x15] 272840 1 T1 1137 T2 136 T4 17
valid_sources[0x16] 250264 1 T1 1064 T2 175 T4 26
valid_sources[0x17] 287922 1 T1 1053 T2 139 T4 13
valid_sources[0x18] 240818 1 T1 1027 T2 150 T4 32
valid_sources[0x19] 250618 1 T1 1219 T2 129 T4 18
valid_sources[0x1a] 249493 1 T1 946 T2 201 T4 23
valid_sources[0x1b] 250452 1 T1 993 T2 136 T4 20
valid_sources[0x1c] 329340 1 T1 1070 T2 119 T4 10
valid_sources[0x1d] 247194 1 T1 1013 T2 236 T4 33
valid_sources[0x1e] 241313 1 T1 988 T2 175 T4 32
valid_sources[0x1f] 238456 1 T1 919 T2 140 T4 23
valid_sources[0x20] 249403 1 T1 936 T2 162 T4 25
valid_sources[0x21] 243354 1 T1 1032 T2 163 T4 29
valid_sources[0x22] 273153 1 T1 969 T2 167 T4 16
valid_sources[0x23] 251020 1 T1 1053 T2 126 T4 29
valid_sources[0x24] 323860 1 T1 987 T2 195 T4 35
valid_sources[0x25] 245626 1 T1 1108 T2 217 T4 24
valid_sources[0x26] 233892 1 T1 922 T2 162 T4 22
valid_sources[0x27] 243834 1 T1 960 T2 187 T4 37
valid_sources[0x28] 764337 1 T1 1011 T2 193 T4 33
valid_sources[0x29] 534691 1 T1 1009 T2 175 T4 21
valid_sources[0x2a] 242297 1 T1 901 T2 142 T4 16
valid_sources[0x2b] 239935 1 T1 1159 T2 220 T4 42
valid_sources[0x2c] 237054 1 T1 1015 T2 181 T4 31
valid_sources[0x2d] 250719 1 T1 933 T2 199 T4 30
valid_sources[0x2e] 1532040 1 T1 1011 T2 136 T4 28
valid_sources[0x2f] 241074 1 T1 1008 T2 159 T4 17
valid_sources[0x30] 245674 1 T1 1106 T2 162 T4 18
valid_sources[0x31] 546010 1 T1 928 T2 139 T4 25
valid_sources[0x32] 233811 1 T1 1052 T2 138 T4 25
valid_sources[0x33] 265891 1 T1 1047 T2 142 T4 34
valid_sources[0x34] 258572 1 T1 984 T2 130 T4 20
valid_sources[0x35] 321265 1 T1 1050 T2 228 T4 24
valid_sources[0x36] 239391 1 T1 1035 T2 149 T4 23
valid_sources[0x37] 328610 1 T1 1065 T2 159 T4 18
valid_sources[0x38] 239349 1 T1 1035 T2 183 T4 19
valid_sources[0x39] 249683 1 T1 1173 T2 159 T4 23
valid_sources[0x3a] 242766 1 T1 1062 T2 171 T4 26
valid_sources[0x3b] 271303 1 T1 1099 T2 150 T4 34
valid_sources[0x3c] 305651 1 T1 1175 T2 123 T4 33
valid_sources[0x3d] 243696 1 T1 975 T2 141 T4 21
valid_sources[0x3e] 240813 1 T1 1095 T2 163 T4 17
valid_sources[0x3f] 243332 1 T1 945 T2 191 T4 52
valid_sources[0x40] 245698 1 T1 1049 T2 175 T4 25
valid_sources[0x41] 306499 1 T1 997 T2 211 T4 32
valid_sources[0x42] 522993 1 T1 1016 T2 174 T4 18
valid_sources[0x43] 247635 1 T1 1068 T2 201 T4 26
valid_sources[0x44] 237261 1 T1 1159 T2 169 T4 36
valid_sources[0x45] 241645 1 T1 1139 T2 178 T4 18
valid_sources[0x46] 242032 1 T1 1196 T2 140 T4 35
valid_sources[0x47] 240561 1 T1 963 T2 209 T4 26
valid_sources[0x48] 251362 1 T1 1247 T2 175 T4 37
valid_sources[0x49] 243978 1 T1 1032 T2 185 T4 31
valid_sources[0x4a] 355556 1 T1 1185 T2 140 T4 21
valid_sources[0x4b] 236735 1 T1 1218 T2 253 T4 12
valid_sources[0x4c] 242598 1 T1 1194 T2 207 T4 23
valid_sources[0x4d] 242815 1 T1 1172 T2 196 T4 14
valid_sources[0x4e] 244602 1 T1 1098 T2 144 T4 12
valid_sources[0x4f] 238283 1 T1 1131 T2 194 T4 43
valid_sources[0x50] 804578 1 T1 1131 T2 174 T4 21
valid_sources[0x51] 247929 1 T1 1093 T2 177 T4 30
valid_sources[0x52] 266953 1 T1 1024 T2 145 T4 34
valid_sources[0x53] 562707 1 T1 949 T2 148 T4 28
valid_sources[0x54] 571840 1 T1 1058 T2 161 T4 26
valid_sources[0x55] 294249 1 T1 954 T2 216 T4 22
valid_sources[0x56] 241132 1 T1 1041 T2 175 T4 26
valid_sources[0x57] 251734 1 T1 1259 T2 214 T4 19
valid_sources[0x58] 539271 1 T1 1126 T2 160 T4 29
valid_sources[0x59] 252203 1 T1 1124 T2 133 T4 22
valid_sources[0x5a] 241047 1 T1 966 T2 202 T4 16
valid_sources[0x5b] 246964 1 T1 1205 T2 210 T4 26
valid_sources[0x5c] 236927 1 T1 1037 T2 167 T4 30
valid_sources[0x5d] 245043 1 T1 1159 T2 147 T4 22
valid_sources[0x5e] 243777 1 T1 972 T2 174 T4 19
valid_sources[0x5f] 2095402 1 T1 1067 T2 179 T4 42
valid_sources[0x60] 248797 1 T1 1081 T2 169 T4 28
valid_sources[0x61] 241711 1 T1 1062 T2 137 T4 23
valid_sources[0x62] 253554 1 T1 990 T2 169 T4 24
valid_sources[0x63] 244005 1 T1 1032 T2 196 T4 18
valid_sources[0x64] 324591 1 T1 993 T2 160 T4 26
valid_sources[0x65] 244265 1 T1 1039 T2 177 T4 22
valid_sources[0x66] 237421 1 T1 1045 T2 129 T4 29
valid_sources[0x67] 2127260 1 T1 1149 T2 106 T4 29
valid_sources[0x68] 239877 1 T1 1179 T2 157 T4 10
valid_sources[0x69] 244974 1 T1 1058 T2 141 T4 16
valid_sources[0x6a] 304708 1 T1 1084 T2 176 T4 34
valid_sources[0x6b] 243041 1 T1 1023 T2 207 T4 22
valid_sources[0x6c] 235346 1 T1 989 T2 210 T4 27
valid_sources[0x6d] 244137 1 T1 1087 T2 151 T4 21
valid_sources[0x6e] 278712 1 T1 1183 T2 124 T4 24
valid_sources[0x6f] 250209 1 T1 1035 T2 186 T4 27
valid_sources[0x70] 2319098 1 T1 1073 T2 150 T4 31
valid_sources[0x71] 281530 1 T1 1089 T2 142 T4 11
valid_sources[0x72] 241902 1 T1 1106 T2 152 T4 21
valid_sources[0x73] 284166 1 T1 1126 T2 213 T4 18
valid_sources[0x74] 244294 1 T1 1136 T2 144 T4 33
valid_sources[0x75] 248642 1 T1 1199 T2 193 T4 30
valid_sources[0x76] 238063 1 T1 1121 T2 159 T4 41
valid_sources[0x77] 247621 1 T1 976 T2 152 T4 21
valid_sources[0x78] 240701 1 T1 1040 T2 96 T4 36
valid_sources[0x79] 248310 1 T1 937 T2 162 T4 30
valid_sources[0x7a] 254310 1 T1 1038 T2 129 T4 36
valid_sources[0x7b] 240946 1 T1 1084 T2 161 T4 26
valid_sources[0x7c] 242800 1 T1 1024 T2 141 T4 28
valid_sources[0x7d] 242372 1 T1 1061 T2 184 T4 34
valid_sources[0x7e] 308959 1 T1 1166 T2 194 T4 22
valid_sources[0x7f] 283957 1 T1 1164 T2 171 T4 27
valid_sources[0x80] 239422 1 T1 1052 T2 126 T4 31



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 19142430 1 T1 68811 T2 3411 T3 40687
values[0x0] all_enables biggest_size 11153395 1 T1 28679 T2 10378 T3 17290
values[0x1] all_enables biggest_size 9596042 1 T1 23355 T2 10314 T3 13941

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%