Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

45230960

1

T1

153827

T2

18953

T3

91306

full_word

40126265

1

T1

120845

T2

24103

T3

71918

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	85356865	1			T1	274672		T2	43056		T3	163224
auto[TlIntgErrCmd]	119	1			T60	7		T61	3		T62	9
auto[TlIntgErrData]	114	1			T60	7		T61	4		T62	5
auto[TlIntgErrBoth]	127	1			T60	6		T61	3		T62	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

39945901

1

T1

137921

T2

20588

T3

81923

auto[1]

45411324

1

T1

136751

T2

22468

T3

81301

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	20711246	1			T1	69110		T2	17177		T3	41236
auto[TlIntgErrNone]	partial	auto[1]	24519387	1			T1	84717		T2	1776		T3	50070
auto[TlIntgErrNone]	full_word	auto[0]	19234494	1			T1	68811		T2	3411		T3	40687
auto[TlIntgErrNone]	full_word	auto[1]	20891738	1			T1	52034		T2	20692		T3	31231
auto[TlIntgErrCmd]	partial	auto[0]	43	1			T60	2		T61	1		T62	1
auto[TlIntgErrCmd]	partial	auto[1]	70	1			T60	5		T61	2		T62	8
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T116	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T117	1		T118	1		T119	1
auto[TlIntgErrData]	partial	auto[0]	57	1			T60	3		T61	1		T62	3
auto[TlIntgErrData]	partial	auto[1]	44	1			T60	3		T61	3		T62	2
auto[TlIntgErrData]	full_word	auto[0]	4	1			T114	1		T120	1		T116	1
auto[TlIntgErrData]	full_word	auto[1]	9	1			T60	1		T121	1		T120	1
auto[TlIntgErrBoth]	partial	auto[0]	50	1			T60	1		T61	2		T121	2
auto[TlIntgErrBoth]	partial	auto[1]	63	1			T60	5		T61	1		T62	4
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T62	1		T121	1		T114	1
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T62	1		T112	1		T120	2