Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00	93.33	100.00	100.00	98.90	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	474500149	2050107	0	0
intr_enable_rd_A	474500149	3297	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474500149	2050107	0	0
T7	191091	39193	0	0
T8	0	157355	0	0
T9	0	60348	0	0
T13	0	106530	0	0
T18	0	86400	0	0
T19	0	191661	0	0
T20	0	172590	0	0
T31	563407	0	0	0
T41	134119	0	0	0
T44	705	0	0	0
T46	567030	0	0	0
T63	0	119800	0	0
T64	0	377764	0	0
T65	0	36	0	0
T66	188828	0	0	0
T67	1422	0	0	0
T68	557041	0	0	0
T69	627727	0	0	0
T70	151000	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474500149	3297	0	0
T8	938942	229	0	0
T11	156402	0	0	0
T13	0	117	0	0
T32	797533	0	0	0
T33	612225	0	0	0
T34	35962	0	0	0
T35	126864	0	0	0
T36	26845	0	0	0
T37	133842	0	0	0
T71	0	33	0	0
T72	0	14	0	0
T73	0	29	0	0
T74	0	35	0	0
T75	0	28	0	0
T76	0	55	0	0
T77	0	23	0	0
T78	0	184	0	0
T79	136106	0	0	0
T80	120562	0	0	0