Unified Coverage Report :: Group :: cip_base_pkg::tl_errors_cg_wrap::tl_errors_cg

Group : cip_base_pkg::tl_errors_cg_wrap::tl_errors_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
86.67	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_errors_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_errors_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_errors_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	2	13	100.00

Variables for Group Instance tl_errors_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_csr_size_err	2	0	2	100.00	100	1	1	2
cp_instr_type_err	2	0	2	100.00	100	1	1	2
cp_mem_byte_access_err	2	1	1	50.00	100	0	0	2
cp_mem_ro_err	2	1	1	50.00	100	0	0	2
cp_mem_wo_err	2	0	2	100.00	100	1	1	2
cp_tl_protocol_err	1	0	1	100.00	100	1	1	0
cp_unmapped_err	2	0	2	100.00	100	1	1	2
cp_write_w_instr_type_err	2	0	2	100.00	100	1	1	2

Summary for Variable cp_csr_size_err

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_csr_size_err

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

869703

1

T8

152935

T9

13937

T10

23271

auto[1]

187488

1

T8

34084

T9

2683

T10

4815

---

Summary for Variable cp_instr_type_err

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_instr_type_err

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

927196

1

T8

164447

T9

14430

T10

24348

auto[1]

129995

1

T8

22572

T9

2190

T10

3738

---

Summary for Variable cp_mem_byte_access_err

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_mem_byte_access_err

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
[auto[1]]	0	0			-	-		-	-		-	-
auto[0]	1057191	0			T8	187019		T9	16620		T10	28086

---

Summary for Variable cp_mem_ro_err

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_mem_ro_err

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
[auto[1]]	0	0			-	-		-	-		-	-
auto[0]	1057191	0			T8	187019		T9	16620		T10	28086

---

Summary for Variable cp_mem_wo_err

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_mem_wo_err

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

949534

1

T8

168050

T9

14807

T10

25494

auto[1]

107657

1

T8

18969

T9

1813

T10

2592

---

Summary for Variable cp_tl_protocol_err

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_tl_protocol_err

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

covered

354143

1

T8

62846

T9

5228

T10

9065

---

Summary for Variable cp_unmapped_err

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_unmapped_err

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1025599

1

T8

181226

T9

16124

T10

27319

auto[1]

31592

1

T8

5793

T9

496

T10

767

---

Summary for Variable cp_write_w_instr_type_err

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write_w_instr_type_err

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

810999

1

T8

144264

T9

12410

T10

20977

auto[1]

246192

1

T8

42755

T9

4210

T10

7109