Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

51200642

1

T1

34019

T2

99614

T3

27252

full_word

45655254

1

T1

26740

T2

78121

T3

24483

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	96855406	1			T1	60759		T2	177735		T3	51735
auto[TlIntgErrCmd]	152	1			T73	11		T74	4		T75	5
auto[TlIntgErrData]	170	1			T73	8		T74	4		T75	4
auto[TlIntgErrBoth]	168	1			T73	11		T74	2		T75	11

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

45679923

1

T1

30544

T2

89335

T3

22885

auto[1]

51175973

1

T1

30215

T2

88400

T3

28850

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	23560345	1			T1	15385		T2	45210		T3	11706
auto[TlIntgErrNone]	partial	auto[1]	27639844	1			T1	18634		T2	54404		T3	15546
auto[TlIntgErrNone]	full_word	auto[0]	22119362	1			T1	15159		T2	44125		T3	11179
auto[TlIntgErrNone]	full_word	auto[1]	23535855	1			T1	11581		T2	33996		T3	13304
auto[TlIntgErrCmd]	partial	auto[0]	56	1			T73	4		T74	1		T75	3
auto[TlIntgErrCmd]	partial	auto[1]	83	1			T73	6		T74	3		T75	2
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T73	1		T126	1		T124	1
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T127	1		T128	3		T129	1
auto[TlIntgErrData]	partial	auto[0]	84	1			T73	8		T74	1		T75	2
auto[TlIntgErrData]	partial	auto[1]	74	1			T74	2		T75	2		T122	5
auto[TlIntgErrData]	full_word	auto[0]	6	1			T74	1		T130	1		T125	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T126	1		T124	2		T127	1
auto[TlIntgErrBoth]	partial	auto[0]	60	1			T73	6		T74	1		T75	5
auto[TlIntgErrBoth]	partial	auto[1]	96	1			T73	4		T74	1		T75	6
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T73	1		T123	2		T131	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T124	1		T132	2		T129	2