Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00	93.33	100.00	100.00	98.90	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	534290881	1766680	0	0
intr_enable_rd_A	534290881	2606	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	534290881	1766680	0	0
T8	158844	320654	0	0
T9	0	27256	0	0
T10	0	45011	0	0
T11	89908	0	0	0
T14	0	60731	0	0
T22	0	156796	0	0
T29	441832	0	0	0
T30	16419	0	0	0
T31	411998	0	0	0
T32	89865	0	0	0
T33	282811	0	0	0
T34	110513	0	0	0
T35	179654	0	0	0
T76	0	577298	0	0
T77	0	142948	0	0
T78	0	222768	0	0
T79	0	40306	0	0
T80	0	76685	0	0
T81	129654	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	534290881	2606	0	0
T9	0	21	0	0
T10	0	86	0	0
T23	112289	0	0	0
T48	0	39	0	0
T53	23319	0	0	0
T61	361124	62	0	0
T66	55302	0	0	0
T67	175797	0	0	0
T68	229313	0	0	0
T69	51364	0	0	0
T70	172402	0	0	0
T71	279769	0	0	0
T72	608373	0	0	0
T82	0	22	0	0
T83	0	3	0	0
T84	0	44	0	0
T85	0	31	0	0
T86	0	69	0	0
T87	0	58	0	0