Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

42138697

1

T1

4116

T2

7811

T3

47475

full_word

38064497

1

T1

9344

T2

11977

T3

37774

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	80202854	1			T1	13460		T2	19788		T3	85249
auto[TlIntgErrCmd]	113	1			T57	7		T58	8		T59	5
auto[TlIntgErrData]	109	1			T57	6		T58	9		T59	2
auto[TlIntgErrBoth]	118	1			T57	7		T58	13		T59	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

37760387

1

T1

5095

T2

8163

T3

42825

auto[1]

42442807

1

T1

8365

T2

11625

T3

42424

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	19388726	1			T1	3124		T2	4204		T3	21416
auto[TlIntgErrNone]	partial	auto[1]	22749657	1			T1	992		T2	3607		T3	26059
auto[TlIntgErrNone]	full_word	auto[0]	18371505	1			T1	1971		T2	3959		T3	21409
auto[TlIntgErrNone]	full_word	auto[1]	19692966	1			T1	7373		T2	8018		T3	16365
auto[TlIntgErrCmd]	partial	auto[0]	42	1			T57	4		T58	3		T59	2
auto[TlIntgErrCmd]	partial	auto[1]	63	1			T57	3		T58	4		T59	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T124	1		T125	1		T126	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T58	1		T120	1		T127	1
auto[TlIntgErrData]	partial	auto[0]	57	1			T57	3		T58	4		T59	1
auto[TlIntgErrData]	partial	auto[1]	43	1			T57	3		T58	5		T59	1
auto[TlIntgErrData]	full_word	auto[0]	3	1			T128	1		T129	1		T123	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T121	1		T129	1		T127	2
auto[TlIntgErrBoth]	partial	auto[0]	49	1			T57	3		T58	5		T59	2
auto[TlIntgErrBoth]	partial	auto[1]	60	1			T57	3		T58	7		T59	1
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T58	1		T130	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T57	1		T122	1		T129	1