Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00	93.33	100.00	100.00	98.90	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	421199750	1320022	0	0
intr_enable_rd_A	421199750	3485	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421199750	1320022	0	0
T7	643139	124101	0	0
T8	0	289406	0	0
T9	0	27044	0	0
T11	0	79148	0	0
T17	0	124780	0	0
T21	0	65939	0	0
T22	0	235360	0	0
T23	93444	0	0	0
T45	38262	0	0	0
T46	778	0	0	0
T54	66808	0	0	0
T55	410162	0	0	0
T56	79869	0	0	0
T61	0	29291	0	0
T62	0	40015	0	0
T63	0	7	0	0
T64	41820	0	0	0
T65	309279	0	0	0
T66	105429	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421199750	3485	0	0
T9	0	62	0	0
T11	0	117	0	0
T16	114973	0	0	0
T44	520178	76	0	0
T47	1198	0	0	0
T67	0	46	0	0
T68	0	35	0	0
T69	0	22	0	0
T70	0	108	0	0
T71	0	98	0	0
T72	0	38	0	0
T73	0	70	0	0
T74	2485	0	0	0
T75	104269	0	0	0
T76	143142	0	0	0
T77	198428	0	0	0
T78	74964	0	0	0
T79	48286	0	0	0
T80	629926	0	0	0