Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	18429434	1			T1	1256		T2	20772		T3	607
all_values[1]	18429434	1			T1	1256		T2	20772		T3	607
all_values[2]	18429434	1			T1	1256		T2	20772		T3	607

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

300968

1

T4

2276

T15

891

T5

6744

auto[1]

54987334

1

T1

3768

T2

62316

T3

1821

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47089766

1

T1

3345

T2

50871

T3

1737

auto[1]

8198536

1

T1

423

T2

11445

T3

84

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	99744	1			T15	891		T8	3536		T27	1571
all_values[0]	auto[0]	auto[1]	422	1			T8	6		T27	6		T89	2
all_values[0]	auto[1]	auto[0]	18309243	1			T1	1236		T2	20763		T3	598
all_values[0]	auto[1]	auto[1]	20025	1			T1	20		T2	9		T3	9
all_values[1]	auto[0]	auto[0]	103685	1			T5	3372		T8	4291		T27	4
all_values[1]	auto[0]	auto[1]	207	1			T8	1		T27	3		T11	25
all_values[1]	auto[1]	auto[0]	18325206	1			T1	1256		T2	20772		T3	607
all_values[1]	auto[1]	auto[1]	336	1			T8	13		T17	1		T27	2
all_values[2]	auto[0]	auto[0]	53024	1			T4	2276		T5	3372		T16	3
all_values[2]	auto[0]	auto[1]	43886	1			T16	19		T8	560		T27	113
all_values[2]	auto[1]	auto[0]	10198864	1			T1	853		T2	9336		T3	532
all_values[2]	auto[1]	auto[1]	8133660	1			T1	403		T2	11436		T3	75