Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	32	0	32	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len_lower_cp	15	0	15	100.00	100	1	1	0
msg_len_upper_cp	1	0	1	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_lower_cross	30	0	30	100.00	100	1	1	0
msg_len_upper_cross	2	0	2	100.00	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

145288

1

T1

26

T2

20

T3

4

auto[1]

141970

1

T1

16

T2

6

T3

12

---

Summary for Variable msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len_lower_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_2050_plus	107753	1			T2	11		T7	22		T14	6
len_1026_2046	7057	1			T6	1		T16	26		T8	139
len_514_1022	6188	1			T1	4		T3	1		T5	1
len_2_510	4172	1			T3	1		T6	7		T16	15
len_2056	209	1			T3	1		T89	3		T69	1
len_2048	337	1			T3	1		T8	3		T17	1
len_2040	199	1			T6	3		T8	2		T50	2
len_1032	194	1			T1	4		T3	2		T8	3
len_1024	2979	1			T1	3		T4	1		T6	1
len_1016	168	1			T6	4		T93	1		T135	1
len_520	184	1			T3	2		T6	2		T50	2
len_512	434	1			T1	3		T4	1		T16	2
len_504	200	1			T1	1		T8	3		T89	2
len_8	1309	1			T4	19		T5	4		T8	6
len_0	12244	1			T1	6		T2	2		T7	13

---

Summary for Variable msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for msg_len_upper_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

len_upper

122

1

T27

1

T92

2

T93

2

---

Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for msg_len_lower_cross

Bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	len_2050_plus	56527	1			T2	9		T7	13		T14	3
auto[0]	len_1026_2046	3790	1			T6	1		T16	11		T8	73
auto[0]	len_514_1022	2786	1			T1	2		T5	1		T6	5
auto[0]	len_2_510	2575	1			T6	4		T16	4		T8	46
auto[0]	len_2056	140	1			T89	2		T11	8		T136	1
auto[0]	len_2048	187	1			T8	3		T17	1		T27	1
auto[0]	len_2040	94	1			T6	3		T50	2		T69	2
auto[0]	len_1032	125	1			T1	3		T3	2		T8	2
auto[0]	len_1024	254	1			T1	1		T6	1		T8	1
auto[0]	len_1016	94	1			T6	2		T93	1		T135	1
auto[0]	len_520	102	1			T6	2		T50	2		T89	1
auto[0]	len_512	253	1			T1	1		T16	1		T8	4
auto[0]	len_504	116	1			T1	1		T8	2		T90	2
auto[0]	len_8	94	1			T69	1		T82	16		T62	2
auto[0]	len_0	5505	1			T1	5		T2	1		T7	8
auto[1]	len_2050_plus	51226	1			T2	2		T7	9		T14	3
auto[1]	len_1026_2046	3267	1			T16	15		T8	66		T17	3
auto[1]	len_514_1022	3402	1			T1	2		T3	1		T16	10
auto[1]	len_2_510	1597	1			T3	1		T6	3		T16	11
auto[1]	len_2056	69	1			T3	1		T89	1		T69	1
auto[1]	len_2048	150	1			T3	1		T27	2		T135	1
auto[1]	len_2040	105	1			T8	2		T69	1		T11	9
auto[1]	len_1032	69	1			T1	1		T8	1		T11	13
auto[1]	len_1024	2725	1			T1	2		T4	1		T16	1
auto[1]	len_1016	74	1			T6	2		T11	2		T76	1
auto[1]	len_520	82	1			T3	2		T93	3		T11	8
auto[1]	len_512	181	1			T1	2		T4	1		T16	1
auto[1]	len_504	84	1			T8	1		T89	2		T90	1
auto[1]	len_8	1215	1			T4	19		T5	4		T8	6
auto[1]	len_0	6739	1			T1	1		T2	1		T7	5

---

Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	0	2	100.00

Automatically Generated Cross Bins for msg_len_upper_cross

Bins

hmac_en

msg_len_upper_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

len_upper

73

1

T92

2

T93

2

T137

1

auto[1]

len_upper

49

1

T27

1

T47

2

T136

1