Group : hmac_env_pkg::hmac_env_cov::status_cg
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Group : hmac_env_pkg::hmac_env_cov::status_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv


Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 20 0 20 100.00
Crosses 192 0 192 100.00


Variables for Group hmac_env_pkg::hmac_env_cov::status_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
digest_swap 2 0 2 100.00 100 1 1 2
endian_swap 2 0 2 100.00 100 1 1 2
hmac_en 2 0 2 100.00 100 1 1 2
key_swap 2 0 2 100.00 100 1 1 2
sta_fifo_depth 8 0 8 100.00 100 1 1 0
sta_fifo_empty 2 0 2 100.00 100 1 1 2
sta_fifo_full 2 0 2 100.00 100 1 1 2


Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
fifo_empty_cross 32 0 32 100.00 100 1 1 0
fifo_full_cross 32 0 32 100.00 100 1 1 0
fifo_depth_cross 128 0 128 100.00 100 1 1 0


Summary for Variable digest_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for digest_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4679834 1 T1 294 T2 2602 T3 40
auto[1] 3074675 1 T1 294 T2 7794 T3 142


Summary for Variable endian_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for endian_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3116675 1 T1 278 T2 6236 T3 60
auto[1] 4637834 1 T1 310 T2 4160 T3 122


Summary for Variable hmac_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hmac_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3261990 1 T1 359 T2 8139 T3 97
auto[1] 4492519 1 T1 229 T2 2257 T3 85


Summary for Variable key_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for key_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4769644 1 T1 326 T2 7094 T3 119
auto[1] 2984865 1 T1 262 T2 3302 T3 63


Summary for Variable sta_fifo_depth

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for sta_fifo_depth

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fifo_depth[0] 7097785 1 T1 540 T2 9682 T3 148
fifo_depth[1] 113430 1 T1 6 T2 111 T3 5
fifo_depth[2] 83204 1 T1 7 T2 127 T3 5
fifo_depth[3] 64286 1 T1 6 T2 114 T3 3
fifo_depth[4] 59533 1 T1 4 T2 114 T3 7
fifo_depth[5] 46976 1 T1 8 T2 89 T3 2
fifo_depth[6] 38348 1 T1 3 T2 73 T3 2
fifo_depth[7] 25373 1 T1 2 T2 39 T3 4


Summary for Variable sta_fifo_empty

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sta_fifo_empty

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 656724 1 T1 48 T2 714 T3 34
auto[1] 7097785 1 T1 540 T2 9682 T3 148


Summary for Variable sta_fifo_full

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sta_fifo_full

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 7742529 1 T1 588 T2 10396 T3 182
auto[1] 11980 1 T8 863 T17 316 T9 392


Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for fifo_empty_cross

Bins
sta_fifo_emptyhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 29230 1 T1 19 T14 193 T23 19
auto[0] auto[0] auto[0] auto[0] auto[1] 28290 1 T7 28 T6 4 T8 2246
auto[0] auto[0] auto[0] auto[1] auto[0] 34891 1 T2 109 T3 5 T8 1067
auto[0] auto[0] auto[0] auto[1] auto[1] 30582 1 T2 117 T5 22 T16 23
auto[0] auto[0] auto[1] auto[0] auto[0] 131941 1 T1 5 T7 1 T5 4
auto[0] auto[0] auto[1] auto[0] auto[1] 31057 1 T2 112 T5 5 T8 468
auto[0] auto[0] auto[1] auto[1] auto[0] 27090 1 T2 116 T3 5 T7 36
auto[0] auto[0] auto[1] auto[1] auto[1] 31833 1 T2 137 T5 2 T6 19
auto[0] auto[1] auto[0] auto[0] auto[0] 40864 1 T4 468 T5 108 T8 2058
auto[0] auto[1] auto[0] auto[0] auto[1] 34126 1 T5 221 T16 22 T8 1683
auto[0] auto[1] auto[0] auto[1] auto[0] 39789 1 T3 7 T14 151 T4 1350
auto[0] auto[1] auto[0] auto[1] auto[1] 41499 1 T1 9 T4 362 T5 170
auto[0] auto[1] auto[1] auto[0] auto[0] 45661 1 T3 2 T4 530 T5 25
auto[0] auto[1] auto[1] auto[0] auto[1] 38819 1 T1 7 T4 19 T5 61
auto[0] auto[1] auto[1] auto[1] auto[0] 38349 1 T1 8 T2 123 T3 15
auto[0] auto[1] auto[1] auto[1] auto[1] 32703 1 T5 51 T23 2 T8 486
auto[1] auto[0] auto[0] auto[0] auto[0] 144972 1 T1 92 T2 261 T7 4
auto[1] auto[0] auto[0] auto[0] auto[1] 164904 1 T1 1 T2 389 T7 1624
auto[1] auto[0] auto[0] auto[1] auto[0] 173251 1 T1 56 T2 3756 T3 18
auto[1] auto[0] auto[0] auto[1] auto[1] 187706 1 T2 386 T7 1 T14 1
auto[1] auto[0] auto[1] auto[0] auto[0] 1731595 1 T1 55 T2 300 T7 683
auto[1] auto[0] auto[1] auto[0] auto[1] 168910 1 T1 50 T2 206 T3 16
auto[1] auto[0] auto[1] auto[1] auto[0] 172646 1 T2 1701 T3 27 T7 1392
auto[1] auto[0] auto[1] auto[1] auto[1] 173092 1 T1 81 T2 549 T3 26
auto[1] auto[1] auto[0] auto[0] auto[0] 538355 1 T2 316 T7 1 T14 1
auto[1] auto[1] auto[0] auto[0] auto[1] 524215 1 T1 50 T2 490 T3 21
auto[1] auto[1] auto[0] auto[1] auto[0] 579054 1 T3 9 T7 1702 T14 953
auto[1] auto[1] auto[0] auto[1] auto[1] 524947 1 T1 51 T2 412 T7 3
auto[1] auto[1] auto[1] auto[0] auto[0] 540271 1 T1 3 T2 24 T3 1
auto[1] auto[1] auto[1] auto[0] auto[1] 486624 1 T1 12 T2 504 T7 1
auto[1] auto[1] auto[1] auto[1] auto[0] 501685 1 T1 88 T2 388 T3 30
auto[1] auto[1] auto[1] auto[1] auto[1] 485558 1 T1 1 T7 1 T4 1277


Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for fifo_full_cross

Bins
sta_fifo_fullhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 173832 1 T1 111 T2 261 T7 4
auto[0] auto[0] auto[0] auto[0] auto[1] 192590 1 T1 1 T2 389 T7 1652
auto[0] auto[0] auto[0] auto[1] auto[0] 206737 1 T1 56 T2 3865 T3 23
auto[0] auto[0] auto[0] auto[1] auto[1] 217658 1 T2 503 T7 1 T14 1
auto[0] auto[0] auto[1] auto[0] auto[0] 1861455 1 T1 60 T2 300 T7 684
auto[0] auto[0] auto[1] auto[0] auto[1] 199077 1 T1 50 T2 318 T3 16
auto[0] auto[0] auto[1] auto[1] auto[0] 199428 1 T2 1817 T3 32 T7 1428
auto[0] auto[0] auto[1] auto[1] auto[1] 203334 1 T1 81 T2 686 T3 26
auto[0] auto[1] auto[0] auto[0] auto[0] 578380 1 T2 316 T7 1 T14 1
auto[0] auto[1] auto[0] auto[0] auto[1] 558281 1 T1 50 T2 490 T3 21
auto[0] auto[1] auto[0] auto[1] auto[0] 618450 1 T3 16 T7 1702 T14 1104
auto[0] auto[1] auto[0] auto[1] auto[1] 566153 1 T1 60 T2 412 T7 3
auto[0] auto[1] auto[1] auto[0] auto[0] 585345 1 T1 3 T2 24 T3 3
auto[0] auto[1] auto[1] auto[0] auto[1] 525090 1 T1 19 T2 504 T7 1
auto[0] auto[1] auto[1] auto[1] auto[0] 538587 1 T1 96 T2 511 T3 45
auto[0] auto[1] auto[1] auto[1] auto[1] 518132 1 T1 1 T7 1 T4 1277
auto[1] auto[0] auto[0] auto[0] auto[0] 370 1 T8 11 T17 24 T9 3
auto[1] auto[0] auto[0] auto[0] auto[1] 604 1 T8 36 T9 7 T11 8
auto[1] auto[0] auto[0] auto[1] auto[0] 1405 1 T8 1 T17 44 T11 3
auto[1] auto[0] auto[0] auto[1] auto[1] 630 1 T8 13 T9 44 T11 123
auto[1] auto[0] auto[1] auto[0] auto[0] 2081 1 T8 29 T9 201 T11 1
auto[1] auto[0] auto[1] auto[0] auto[1] 890 1 T11 2 T13 10 T140 10
auto[1] auto[0] auto[1] auto[1] auto[0] 308 1 T8 13 T17 9 T141 6
auto[1] auto[0] auto[1] auto[1] auto[1] 1591 1 T8 1 T9 81 T13 8
auto[1] auto[1] auto[0] auto[0] auto[0] 839 1 T8 217 T17 45 T13 2
auto[1] auto[1] auto[0] auto[0] auto[1] 60 1 T8 34 T141 2 T142 1
auto[1] auto[1] auto[0] auto[1] auto[0] 393 1 T8 370 T13 1 T70 8
auto[1] auto[1] auto[0] auto[1] auto[1] 293 1 T8 93 T17 22 T9 51
auto[1] auto[1] auto[1] auto[0] auto[0] 587 1 T8 1 T17 172 T11 43
auto[1] auto[1] auto[1] auto[0] auto[1] 353 1 T11 75 T13 5 T143 1
auto[1] auto[1] auto[1] auto[1] auto[0] 1447 1 T8 44 T11 146 T13 86
auto[1] auto[1] auto[1] auto[1] auto[1] 129 1 T9 5 T11 63 T144 33


Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 128 0 128 100.00


Automatically Generated Cross Bins for fifo_depth_cross

Bins
sta_fifo_depthhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fifo_depth[0] auto[0] auto[0] auto[0] auto[0] 144972 1 T1 92 T2 261 T7 4
fifo_depth[0] auto[0] auto[0] auto[0] auto[1] 164904 1 T1 1 T2 389 T7 1624
fifo_depth[0] auto[0] auto[0] auto[1] auto[0] 173251 1 T1 56 T2 3756 T3 18
fifo_depth[0] auto[0] auto[0] auto[1] auto[1] 187706 1 T2 386 T7 1 T14 1
fifo_depth[0] auto[0] auto[1] auto[0] auto[0] 1731595 1 T1 55 T2 300 T7 683
fifo_depth[0] auto[0] auto[1] auto[0] auto[1] 168910 1 T1 50 T2 206 T3 16
fifo_depth[0] auto[0] auto[1] auto[1] auto[0] 172646 1 T2 1701 T3 27 T7 1392
fifo_depth[0] auto[0] auto[1] auto[1] auto[1] 173092 1 T1 81 T2 549 T3 26
fifo_depth[0] auto[1] auto[0] auto[0] auto[0] 538355 1 T2 316 T7 1 T14 1
fifo_depth[0] auto[1] auto[0] auto[0] auto[1] 524215 1 T1 50 T2 490 T3 21
fifo_depth[0] auto[1] auto[0] auto[1] auto[0] 579054 1 T3 9 T7 1702 T14 953
fifo_depth[0] auto[1] auto[0] auto[1] auto[1] 524947 1 T1 51 T2 412 T7 3
fifo_depth[0] auto[1] auto[1] auto[0] auto[0] 540271 1 T1 3 T2 24 T3 1
fifo_depth[0] auto[1] auto[1] auto[0] auto[1] 486624 1 T1 12 T2 504 T7 1
fifo_depth[0] auto[1] auto[1] auto[1] auto[0] 501685 1 T1 88 T2 388 T3 30
fifo_depth[0] auto[1] auto[1] auto[1] auto[1] 485558 1 T1 1 T7 1 T4 1277
fifo_depth[1] auto[0] auto[0] auto[0] auto[0] 2796 1 T1 3 T14 78 T23 14
fifo_depth[1] auto[0] auto[0] auto[0] auto[1] 3133 1 T7 27 T8 103 T17 8
fifo_depth[1] auto[0] auto[0] auto[1] auto[0] 3479 1 T2 14 T3 1 T8 86
fifo_depth[1] auto[0] auto[0] auto[1] auto[1] 3849 1 T2 18 T5 17 T8 122
fifo_depth[1] auto[0] auto[1] auto[0] auto[0] 37715 1 T7 1 T5 4 T8 17
fifo_depth[1] auto[0] auto[1] auto[0] auto[1] 3328 1 T2 20 T5 3 T8 34
fifo_depth[1] auto[0] auto[1] auto[1] auto[0] 3302 1 T2 13 T3 2 T7 27
fifo_depth[1] auto[0] auto[1] auto[1] auto[1] 3101 1 T2 31 T5 2 T6 3
fifo_depth[1] auto[1] auto[0] auto[0] auto[0] 6817 1 T4 78 T5 83 T8 122
fifo_depth[1] auto[1] auto[0] auto[0] auto[1] 6427 1 T5 162 T16 22 T8 73
fifo_depth[1] auto[1] auto[0] auto[1] auto[0] 6952 1 T14 74 T4 202 T5 52
fifo_depth[1] auto[1] auto[0] auto[1] auto[1] 6473 1 T1 2 T4 71 T5 133
fifo_depth[1] auto[1] auto[1] auto[0] auto[0] 8251 1 T3 1 T4 92 T5 18
fifo_depth[1] auto[1] auto[1] auto[0] auto[1] 6359 1 T4 2 T5 51 T8 161
fifo_depth[1] auto[1] auto[1] auto[1] auto[0] 5874 1 T1 1 T2 15 T3 1
fifo_depth[1] auto[1] auto[1] auto[1] auto[1] 5574 1 T5 31 T23 2 T8 78
fifo_depth[2] auto[0] auto[0] auto[0] auto[0] 2231 1 T1 4 T14 69 T23 5
fifo_depth[2] auto[0] auto[0] auto[0] auto[1] 2351 1 T7 1 T8 103 T17 64
fifo_depth[2] auto[0] auto[0] auto[1] auto[0] 2914 1 T2 19 T3 1 T8 95
fifo_depth[2] auto[0] auto[0] auto[1] auto[1] 3214 1 T2 19 T5 5 T16 23
fifo_depth[2] auto[0] auto[1] auto[0] auto[0] 22961 1 T1 1 T8 32 T26 16
fifo_depth[2] auto[0] auto[1] auto[0] auto[1] 2700 1 T2 19 T5 2 T8 95
fifo_depth[2] auto[0] auto[1] auto[1] auto[0] 2296 1 T2 18 T3 1 T7 8
fifo_depth[2] auto[0] auto[1] auto[1] auto[1] 2256 1 T2 31 T6 4 T8 118
fifo_depth[2] auto[1] auto[0] auto[0] auto[0] 5512 1 T4 95 T5 23 T8 111
fifo_depth[2] auto[1] auto[0] auto[0] auto[1] 4790 1 T5 48 T8 79 T26 3
fifo_depth[2] auto[1] auto[0] auto[1] auto[0] 5709 1 T3 1 T14 59 T4 210
fifo_depth[2] auto[1] auto[0] auto[1] auto[1] 5056 1 T1 1 T4 61 T5 31
fifo_depth[2] auto[1] auto[1] auto[0] auto[0] 6506 1 T4 96 T5 5 T8 108
fifo_depth[2] auto[1] auto[1] auto[0] auto[1] 5195 1 T4 3 T5 7 T6 1
fifo_depth[2] auto[1] auto[1] auto[1] auto[0] 4929 1 T1 1 T2 21 T3 2
fifo_depth[2] auto[1] auto[1] auto[1] auto[1] 4584 1 T5 16 T8 93 T27 25
fifo_depth[3] auto[0] auto[0] auto[0] auto[0] 1549 1 T1 4 T14 38 T16 1
fifo_depth[3] auto[0] auto[0] auto[0] auto[1] 1693 1 T6 1 T8 110 T17 13
fifo_depth[3] auto[0] auto[0] auto[1] auto[0] 1945 1 T2 15 T8 74 T27 4
fifo_depth[3] auto[0] auto[0] auto[1] auto[1] 2513 1 T2 15 T8 124 T27 3
fifo_depth[3] auto[0] auto[1] auto[0] auto[0] 16500 1 T1 2 T8 33 T26 4
fifo_depth[3] auto[0] auto[1] auto[0] auto[1] 1874 1 T2 22 T8 37 T27 2
fifo_depth[3] auto[0] auto[1] auto[1] auto[0] 1700 1 T2 15 T6 1 T8 99
fifo_depth[3] auto[0] auto[1] auto[1] auto[1] 1644 1 T2 27 T6 4 T8 94
fifo_depth[3] auto[1] auto[0] auto[0] auto[0] 4631 1 T4 86 T5 2 T8 121
fifo_depth[3] auto[1] auto[0] auto[0] auto[1] 3870 1 T5 9 T8 51 T49 85
fifo_depth[3] auto[1] auto[0] auto[1] auto[0] 4777 1 T14 15 T4 202 T5 2
fifo_depth[3] auto[1] auto[0] auto[1] auto[1] 4443 1 T4 72 T5 6 T6 1
fifo_depth[3] auto[1] auto[1] auto[0] auto[0] 5342 1 T4 95 T5 2 T8 119
fifo_depth[3] auto[1] auto[1] auto[0] auto[1] 4176 1 T4 3 T5 3 T8 159
fifo_depth[3] auto[1] auto[1] auto[1] auto[0] 4017 1 T2 20 T3 3 T14 8
fifo_depth[3] auto[1] auto[1] auto[1] auto[1] 3612 1 T5 4 T8 76 T27 2
fifo_depth[4] auto[0] auto[0] auto[0] auto[0] 1784 1 T1 2 T14 8 T16 11
fifo_depth[4] auto[0] auto[0] auto[0] auto[1] 1691 1 T6 2 T8 94 T17 65
fifo_depth[4] auto[0] auto[0] auto[1] auto[0] 2111 1 T2 13 T3 2 T8 67
fifo_depth[4] auto[0] auto[0] auto[1] auto[1] 2535 1 T2 19 T8 114 T27 4
fifo_depth[4] auto[0] auto[1] auto[0] auto[0] 12574 1 T1 1 T8 70 T17 9
fifo_depth[4] auto[0] auto[1] auto[0] auto[1] 2119 1 T2 22 T8 90 T92 8
fifo_depth[4] auto[0] auto[1] auto[1] auto[0] 1697 1 T2 20 T3 1 T7 1
fifo_depth[4] auto[0] auto[1] auto[1] auto[1] 1619 1 T2 25 T6 1 T8 99
fifo_depth[4] auto[1] auto[0] auto[0] auto[0] 4361 1 T4 82 T8 129 T27 9
fifo_depth[4] auto[1] auto[0] auto[0] auto[1] 3817 1 T5 2 T8 67 T49 101
fifo_depth[4] auto[1] auto[0] auto[1] auto[0] 4560 1 T3 1 T14 3 T4 194
fifo_depth[4] auto[1] auto[0] auto[1] auto[1] 4183 1 T4 64 T8 34 T17 11
fifo_depth[4] auto[1] auto[1] auto[0] auto[0] 4912 1 T3 1 T4 85 T8 179
fifo_depth[4] auto[1] auto[1] auto[0] auto[1] 4100 1 T1 1 T4 3 T8 157
fifo_depth[4] auto[1] auto[1] auto[1] auto[0] 3973 1 T2 15 T3 2 T14 6
fifo_depth[4] auto[1] auto[1] auto[1] auto[1] 3497 1 T8 90 T49 93 T92 3
fifo_depth[5] auto[0] auto[0] auto[0] auto[0] 1190 1 T1 5 T16 1 T8 19
fifo_depth[5] auto[0] auto[0] auto[0] auto[1] 1297 1 T6 1 T8 85 T17 17
fifo_depth[5] auto[0] auto[0] auto[1] auto[0] 1520 1 T2 16 T3 1 T8 57
fifo_depth[5] auto[0] auto[0] auto[1] auto[1] 1760 1 T2 20 T8 95 T27 1
fifo_depth[5] auto[0] auto[1] auto[0] auto[0] 9070 1 T1 1 T8 56 T17 9
fifo_depth[5] auto[0] auto[1] auto[0] auto[1] 1547 1 T2 11 T8 25 T92 2
fifo_depth[5] auto[0] auto[1] auto[1] auto[0] 1285 1 T2 20 T3 1 T8 133
fifo_depth[5] auto[0] auto[1] auto[1] auto[1] 1203 1 T2 11 T6 1 T8 48
fifo_depth[5] auto[1] auto[0] auto[0] auto[0] 3591 1 T4 63 T8 100 T92 1
fifo_depth[5] auto[1] auto[0] auto[0] auto[1] 3265 1 T8 76 T49 93 T11 184
fifo_depth[5] auto[1] auto[0] auto[1] auto[0] 4030 1 T4 187 T8 79 T49 101
fifo_depth[5] auto[1] auto[0] auto[1] auto[1] 3667 1 T1 1 T4 43 T6 1
fifo_depth[5] auto[1] auto[1] auto[0] auto[0] 4018 1 T4 84 T8 91 T49 106
fifo_depth[5] auto[1] auto[1] auto[0] auto[1] 3278 1 T1 1 T4 4 T8 135
fifo_depth[5] auto[1] auto[1] auto[1] auto[0] 3365 1 T2 11 T4 187 T15 1
fifo_depth[5] auto[1] auto[1] auto[1] auto[1] 2890 1 T8 65 T49 98 T9 2
fifo_depth[6] auto[0] auto[0] auto[0] auto[0] 1213 1 T1 1 T8 104 T17 4
fifo_depth[6] auto[0] auto[0] auto[0] auto[1] 999 1 T8 55 T17 61 T27 1
fifo_depth[6] auto[0] auto[0] auto[1] auto[0] 1596 1 T2 15 T8 53 T27 1
fifo_depth[6] auto[0] auto[0] auto[1] auto[1] 1387 1 T2 12 T8 86 T92 1
fifo_depth[6] auto[0] auto[1] auto[0] auto[0] 6647 1 T8 39 T17 9 T9 2
fifo_depth[6] auto[0] auto[1] auto[0] auto[1] 1325 1 T2 11 T8 91 T27 2
fifo_depth[6] auto[0] auto[1] auto[1] auto[0] 1144 1 T2 14 T6 1 T8 150
fifo_depth[6] auto[0] auto[1] auto[1] auto[1] 936 1 T2 8 T6 3 T8 51
fifo_depth[6] auto[1] auto[0] auto[0] auto[0] 2952 1 T4 41 T8 71 T17 1
fifo_depth[6] auto[1] auto[0] auto[0] auto[1] 2652 1 T8 76 T49 76 T92 1
fifo_depth[6] auto[1] auto[0] auto[1] auto[0] 3173 1 T3 1 T4 154 T6 4
fifo_depth[6] auto[1] auto[0] auto[1] auto[1] 3003 1 T4 29 T8 29 T17 2
fifo_depth[6] auto[1] auto[1] auto[0] auto[0] 3499 1 T4 47 T8 134 T49 92
fifo_depth[6] auto[1] auto[1] auto[0] auto[1] 2607 1 T1 1 T4 2 T6 2
fifo_depth[6] auto[1] auto[1] auto[1] auto[0] 2676 1 T1 1 T2 13 T3 1
fifo_depth[6] auto[1] auto[1] auto[1] auto[1] 2539 1 T8 41 T49 71 T9 24
fifo_depth[7] auto[0] auto[0] auto[0] auto[0] 706 1 T8 41 T17 1 T11 13
fifo_depth[7] auto[0] auto[0] auto[0] auto[1] 705 1 T8 28 T17 8 T92 1
fifo_depth[7] auto[0] auto[0] auto[1] auto[0] 960 1 T2 7 T8 37 T11 114
fifo_depth[7] auto[0] auto[0] auto[1] auto[1] 809 1 T2 5 T8 60 T92 1
fifo_depth[7] auto[0] auto[1] auto[0] auto[0] 4030 1 T8 63 T17 8 T9 1
fifo_depth[7] auto[0] auto[1] auto[0] auto[1] 1006 1 T2 7 T8 33 T11 98
fifo_depth[7] auto[0] auto[1] auto[1] auto[0] 754 1 T2 7 T8 108 T17 36
fifo_depth[7] auto[0] auto[1] auto[1] auto[1] 662 1 T2 1 T6 1 T8 32
fifo_depth[7] auto[1] auto[0] auto[0] auto[0] 1955 1 T4 13 T8 53 T27 1
fifo_depth[7] auto[1] auto[0] auto[0] auto[1] 1896 1 T8 70 T49 59 T11 107
fifo_depth[7] auto[1] auto[0] auto[1] auto[0] 2174 1 T3 1 T4 80 T6 2
fifo_depth[7] auto[1] auto[0] auto[1] auto[1] 2005 1 T1 1 T4 16 T6 1
fifo_depth[7] auto[1] auto[1] auto[0] auto[0] 2428 1 T4 22 T8 70 T49 52
fifo_depth[7] auto[1] auto[1] auto[0] auto[1] 1852 1 T1 1 T4 2 T6 1
fifo_depth[7] auto[1] auto[1] auto[1] auto[0] 1806 1 T2 12 T3 3 T4 119
fifo_depth[7] auto[1] auto[1] auto[1] auto[1] 1625 1 T8 26 T49 46 T9 6

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