Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	18429434	1			T1	1256		T2	20772		T3	607
all_pins[1]	18429434	1			T1	1256		T2	20772		T3	607
all_pins[2]	18429434	1			T1	1256		T2	20772		T3	607

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	47133459	1			T1	3344		T2	50870		T3	1735
values[0x1]	8154843	1			T1	424		T2	11446		T3	86
transitions[0x0=>0x1]	8154679	1			T1	424		T2	11446		T3	86
transitions[0x1=>0x0]	8154691	1			T1	424		T2	11446		T3	86

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	18408616	1			T1	1235		T2	20762		T3	596
all_pins[0]	values[0x1]	20818	1			T1	21		T2	10		T3	11
all_pins[0]	transitions[0x0=>0x1]	20752	1			T1	21		T2	10		T3	11
all_pins[0]	transitions[0x1=>0x0]	8133606	1			T1	403		T2	11436		T3	75
all_pins[1]	values[0x0]	18429069	1			T1	1256		T2	20772		T3	607
all_pins[1]	values[0x1]	365	1			T8	19		T17	1		T27	2
all_pins[1]	transitions[0x0=>0x1]	311	1			T8	17		T17	1		T27	1
all_pins[1]	transitions[0x1=>0x0]	20764	1			T1	21		T2	10		T3	11
all_pins[2]	values[0x0]	10295774	1			T1	853		T2	9336		T3	532
all_pins[2]	values[0x1]	8133660	1			T1	403		T2	11436		T3	75
all_pins[2]	transitions[0x0=>0x1]	8133616	1			T1	403		T2	11436		T3	75
all_pins[2]	transitions[0x1=>0x0]	321	1			T8	19		T17	1		T27	1