Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 1022 1 T8 17 T27 17 T11 114
all_values[1] 1022 1 T8 17 T27 17 T11 114
all_values[2] 1022 1 T8 17 T27 17 T11 114


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1543 1 T8 20 T27 26 T11 172
auto[1] 1523 1 T8 31 T27 25 T11 170


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1109 1 T8 22 T27 27 T11 115
auto[1] 1957 1 T8 29 T27 24 T11 227


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1744 1 T8 32 T27 32 T11 191
auto[1] 1322 1 T8 19 T27 19 T11 151


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 197 1 T8 5 T27 8 T11 21
all_values[0] auto[0] auto[0] auto[1] 104 1 T8 1 T11 12 T76 2
all_values[0] auto[0] auto[1] auto[0] 163 1 T8 2 T27 2 T11 13
all_values[0] auto[0] auto[1] auto[1] 101 1 T8 3 T27 1 T11 15
all_values[0] auto[1] auto[0] auto[1] 228 1 T8 3 T27 3 T11 30
all_values[0] auto[1] auto[1] auto[1] 229 1 T8 3 T27 3 T11 23
all_values[1] auto[0] auto[0] auto[0] 170 1 T8 2 T27 4 T11 18
all_values[1] auto[0] auto[0] auto[1] 118 1 T27 2 T11 11 T76 1
all_values[1] auto[0] auto[1] auto[0] 188 1 T8 6 T27 6 T11 26
all_values[1] auto[0] auto[1] auto[1] 136 1 T8 4 T11 15 T76 2
all_values[1] auto[1] auto[0] auto[1] 229 1 T8 1 T27 3 T11 31
all_values[1] auto[1] auto[1] auto[1] 181 1 T8 4 T27 2 T11 13
all_values[2] auto[0] auto[0] auto[0] 190 1 T8 2 T27 2 T11 17
all_values[2] auto[0] auto[0] auto[1] 87 1 T8 1 T27 1 T11 9
all_values[2] auto[0] auto[1] auto[0] 201 1 T8 5 T27 5 T11 20
all_values[2] auto[0] auto[1] auto[1] 89 1 T8 1 T27 1 T11 14
all_values[2] auto[1] auto[0] auto[1] 220 1 T8 5 T27 3 T11 23
all_values[2] auto[1] auto[1] auto[1] 235 1 T8 3 T27 5 T11 31


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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