Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	90	0	90	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	0	5	100.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	0	7	100.00	100	1	1	0
key_swap	2	0	2	100.00	100	1	1	2
sha_en	2	0	2	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	16	0	16	100.00	100	1	1	0
hmac_dis_x_sha_en	4	0	4	100.00	100	1	1	0
key_x_digest_mismatch	35	0	35	100.00	100	1	1	0
key_length_x_digest_size	35	0	35	100.00	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for digest_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_invalid	4116	1			T1	5		T2	10		T3	2
sha2_none	4316	1			T1	13		T2	4		T3	1
sha2_512	7722	1			T1	7		T2	4		T3	4
sha2_384	7453	1			T1	4		T2	2		T3	2
sha2_256	6289	1			T1	5		T2	3		T3	2

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18842

1

T1

19

T2

10

T3

3

auto[1]

11422

1

T1

15

T2

13

T3

8

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11356

1

T1

14

T2

13

T3

3

auto[1]

18908

1

T1

20

T2

10

T3

8

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

15895

1

T1

14

T2

6

T3

5

disabled

14369

1

T1

20

T2

17

T3

6

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for key_length

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	4508	1			T1	4		T2	2		T3	1
key_none	7746	1			T1	4		T2	4		T7	4
key_1024	4404	1			T1	3		T2	2		T3	1
key_512	3854	1			T1	5		T2	2		T3	1
key_384	3451	1			T1	6		T2	4		T3	4
key_256	3183	1			T1	5		T2	5		T3	1
key_128	3038	1			T1	7		T2	4		T3	3

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18874

1

T1

18

T2

12

T3

6

auto[1]

11390

1

T1

16

T2

11

T3

5

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

30106

1

T1

34

T2

23

T3

11

disabled

158

1

T7

1

T5

1

T8

3

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

auto[0]

auto[0]

auto[0]

1652

1

T2

1

T7

2

T4

9

enabled

auto[0]

auto[0]

auto[1]

1637

1

T1

2

T2

1

T3

1

enabled

auto[0]

auto[1]

auto[0]

1629

1

T3

1

T7

3

T14

2

enabled

auto[0]

auto[1]

auto[1]

1651

1

T1

3

T2

1

T7

1

enabled

auto[1]

auto[0]

auto[0]

4345

1

T1

3

T2

1

T3

1

enabled

auto[1]

auto[0]

auto[1]

1627

1

T1

1

T2

1

T4

6

enabled

auto[1]

auto[1]

auto[0]

1763

1

T1

4

T2

1

T3

2

enabled

auto[1]

auto[1]

auto[1]

1591

1

T1

1

T4

2

T5

6

disabled

auto[0]

auto[0]

auto[0]

1148

1

T1

4

T2

2

T7

4

disabled

auto[0]

auto[0]

auto[1]

1218

1

T1

1

T2

1

T7

3

disabled

auto[0]

auto[1]

auto[0]

1179

1

T1

4

T2

4

T3

1

disabled

auto[0]

auto[1]

auto[1]

1242

1

T2

3

T15

1

T5

4

disabled

auto[1]

auto[0]

auto[0]

5984

1

T1

3

T2

1

T7

2

disabled

auto[1]

auto[0]

auto[1]

1231

1

T1

5

T2

2

T3

1

disabled

auto[1]

auto[1]

auto[0]

1174

1

T2

2

T3

1

T7

4

disabled

auto[1]

auto[1]

auto[1]

1193

1

T1

3

T2

2

T3

3

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

15837

1

T1

14

T2

6

T3

5

enabled

disabled

58

1

T11

1

T77

1

T78

1

disabled

disabled

100

1

T7

1

T5

1

T8

3

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

14269

1

T1

20

T2

17

T3

6

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	0	35	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	979	1			T1	1		T2	1		T7	4
key_invalid	sha2_none	845	1			T1	2		T7	1		T15	1
key_invalid	sha2_512	901	1			T7	3		T4	1		T5	3
key_invalid	sha2_384	881	1			T1	1		T2	1		T3	1
key_invalid	sha2_256	817	1			T7	1		T4	1		T6	2
key_none	sha2_invalid	502	1			T1	2		T2	2		T7	1
key_none	sha2_none	514	1			T2	2		T5	1		T6	1
key_none	sha2_512	2563	1			T1	1		T4	2		T5	2
key_none	sha2_384	2563	1			T7	2		T4	1		T15	1
key_none	sha2_256	1564	1			T1	1		T7	1		T14	1
key_1024	sha2_invalid	524	1			T1	1		T4	1		T23	2
key_1024	sha2_none	604	1			T1	1		T4	1		T5	1
key_1024	sha2_512	1769	1			T2	1		T3	1		T7	2
key_1024	sha2_384	918	1			T1	1		T7	1		T4	1
key_512	sha2_invalid	530	1			T2	1		T7	1		T14	1
key_512	sha2_none	581	1			T1	1		T4	4		T5	3
key_512	sha2_512	604	1			T1	2		T2	1		T4	5
key_512	sha2_384	1228	1			T1	2		T4	1		T15	1
key_512	sha2_256	867	1			T3	1		T4	2		T23	1
key_384	sha2_invalid	501	1			T2	2		T3	1		T6	1
key_384	sha2_none	598	1			T1	2		T2	1		T5	1
key_384	sha2_512	616	1			T1	2		T3	2		T14	1
key_384	sha2_384	604	1			T3	1		T7	1		T4	3
key_384	sha2_256	1079	1			T1	2		T2	1		T7	1
key_256	sha2_invalid	556	1			T2	2		T4	1		T6	1
key_256	sha2_none	547	1			T1	3		T7	2		T4	1
key_256	sha2_512	637	1			T2	1		T3	1		T7	1
key_256	sha2_384	628	1			T2	1		T14	1		T4	2
key_256	sha2_256	765	1			T1	2		T2	1		T14	1
key_128	sha2_invalid	512	1			T1	1		T2	2		T3	1
key_128	sha2_none	613	1			T1	4		T2	1		T3	1
key_128	sha2_512	615	1			T1	2		T2	1		T7	2
key_128	sha2_384	617	1			T7	1		T14	1		T5	2
key_128	sha2_256	638	1			T3	1		T7	2		T14	1

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

540

1

T2

1

T4

2

T6

1

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	0	35	100.00

Automatically Generated Cross Bins for key_length_x_digest_size

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	979	1			T1	1		T2	1		T7	4
key_invalid	sha2_none	845	1			T1	2		T7	1		T15	1
key_invalid	sha2_512	901	1			T7	3		T4	1		T5	3
key_invalid	sha2_384	881	1			T1	1		T2	1		T3	1
key_invalid	sha2_256	817	1			T7	1		T4	1		T6	2
key_none	sha2_invalid	502	1			T1	2		T2	2		T7	1
key_none	sha2_none	514	1			T2	2		T5	1		T6	1
key_none	sha2_512	2563	1			T1	1		T4	2		T5	2
key_none	sha2_384	2563	1			T7	2		T4	1		T15	1
key_none	sha2_256	1564	1			T1	1		T7	1		T14	1
key_1024	sha2_invalid	524	1			T1	1		T4	1		T23	2
key_1024	sha2_none	604	1			T1	1		T4	1		T5	1
key_1024	sha2_512	1769	1			T2	1		T3	1		T7	2
key_1024	sha2_384	918	1			T1	1		T7	1		T4	1
key_1024	sha2_256	540	1			T2	1		T4	2		T6	1
key_512	sha2_invalid	530	1			T2	1		T7	1		T14	1
key_512	sha2_none	581	1			T1	1		T4	4		T5	3
key_512	sha2_512	604	1			T1	2		T2	1		T4	5
key_512	sha2_384	1228	1			T1	2		T4	1		T15	1
key_512	sha2_256	867	1			T3	1		T4	2		T23	1
key_384	sha2_invalid	501	1			T2	2		T3	1		T6	1
key_384	sha2_none	598	1			T1	2		T2	1		T5	1
key_384	sha2_512	616	1			T1	2		T3	2		T14	1
key_384	sha2_384	604	1			T3	1		T7	1		T4	3
key_384	sha2_256	1079	1			T1	2		T2	1		T7	1
key_256	sha2_invalid	556	1			T2	2		T4	1		T6	1
key_256	sha2_none	547	1			T1	3		T7	2		T4	1
key_256	sha2_512	637	1			T2	1		T3	1		T7	1
key_256	sha2_384	628	1			T2	1		T14	1		T4	2
key_256	sha2_256	765	1			T1	2		T2	1		T14	1
key_128	sha2_invalid	512	1			T1	1		T2	2		T3	1
key_128	sha2_none	613	1			T1	4		T2	1		T3	1
key_128	sha2_512	615	1			T1	2		T2	1		T7	2
key_128	sha2_384	617	1			T7	1		T14	1		T5	2
key_128	sha2_256	638	1			T3	1		T7	2		T14	1