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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.61 95.40 97.17 100.00 94.12 98.27 98.48 99.85


Total test records in report: 660
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T533 /workspace/coverage/cover_reg_top/23.hmac_intr_test.624537619 Aug 09 07:16:00 PM PDT 24 Aug 09 07:16:01 PM PDT 24 18025380 ps
T534 /workspace/coverage/cover_reg_top/37.hmac_intr_test.603941165 Aug 09 07:15:52 PM PDT 24 Aug 09 07:15:53 PM PDT 24 12727194 ps
T535 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.2819540838 Aug 09 07:15:48 PM PDT 24 Aug 09 07:15:51 PM PDT 24 96770414 ps
T536 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.3214188517 Aug 09 07:15:43 PM PDT 24 Aug 09 07:15:44 PM PDT 24 459479987 ps
T537 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.4125045602 Aug 09 07:16:05 PM PDT 24 Aug 09 07:31:14 PM PDT 24 92701320774 ps
T114 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.2445077096 Aug 09 07:15:50 PM PDT 24 Aug 09 07:15:52 PM PDT 24 68958492 ps
T67 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.3009729541 Aug 09 07:15:54 PM PDT 24 Aug 09 07:15:57 PM PDT 24 446836430 ps
T538 /workspace/coverage/cover_reg_top/22.hmac_intr_test.3718032028 Aug 09 07:15:59 PM PDT 24 Aug 09 07:16:00 PM PDT 24 21253056 ps
T68 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.2393490714 Aug 09 07:15:51 PM PDT 24 Aug 09 07:15:53 PM PDT 24 167275915 ps
T539 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.3417133313 Aug 09 07:15:58 PM PDT 24 Aug 09 07:16:00 PM PDT 24 475476605 ps
T540 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.302941422 Aug 09 07:16:03 PM PDT 24 Aug 09 07:16:06 PM PDT 24 730795119 ps
T541 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.3943584395 Aug 09 07:15:45 PM PDT 24 Aug 09 07:16:01 PM PDT 24 4206377824 ps
T100 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.3640239772 Aug 09 07:15:50 PM PDT 24 Aug 09 07:15:51 PM PDT 24 31937103 ps
T542 /workspace/coverage/cover_reg_top/33.hmac_intr_test.3942646877 Aug 09 07:15:52 PM PDT 24 Aug 09 07:15:53 PM PDT 24 56370852 ps
T115 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.679497902 Aug 09 07:15:59 PM PDT 24 Aug 09 07:16:01 PM PDT 24 185358186 ps
T543 /workspace/coverage/cover_reg_top/11.hmac_intr_test.59086602 Aug 09 07:16:03 PM PDT 24 Aug 09 07:16:04 PM PDT 24 25873805 ps
T544 /workspace/coverage/cover_reg_top/18.hmac_intr_test.394124741 Aug 09 07:16:00 PM PDT 24 Aug 09 07:16:00 PM PDT 24 42145592 ps
T101 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.4119717505 Aug 09 07:15:51 PM PDT 24 Aug 09 07:15:52 PM PDT 24 23053965 ps
T545 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.594405691 Aug 09 07:15:57 PM PDT 24 Aug 09 07:19:58 PM PDT 24 48194303871 ps
T116 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.2850213828 Aug 09 07:16:03 PM PDT 24 Aug 09 07:16:05 PM PDT 24 113669113 ps
T546 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.1256163769 Aug 09 07:15:58 PM PDT 24 Aug 09 07:16:02 PM PDT 24 353688782 ps
T102 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.2891818498 Aug 09 07:15:53 PM PDT 24 Aug 09 07:16:01 PM PDT 24 554156949 ps
T547 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.1169226165 Aug 09 07:15:48 PM PDT 24 Aug 09 07:15:51 PM PDT 24 242549716 ps
T548 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.2063834565 Aug 09 07:16:04 PM PDT 24 Aug 09 07:16:06 PM PDT 24 316773397 ps
T549 /workspace/coverage/cover_reg_top/48.hmac_intr_test.3880255844 Aug 09 07:16:04 PM PDT 24 Aug 09 07:16:05 PM PDT 24 23206769 ps
T550 /workspace/coverage/cover_reg_top/25.hmac_intr_test.3075166631 Aug 09 07:16:00 PM PDT 24 Aug 09 07:16:01 PM PDT 24 35995342 ps
T103 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.3498130661 Aug 09 07:16:01 PM PDT 24 Aug 09 07:16:17 PM PDT 24 1644837438 ps
T551 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.1651146618 Aug 09 07:15:47 PM PDT 24 Aug 09 07:15:58 PM PDT 24 736175217 ps
T552 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.2249899755 Aug 09 07:16:10 PM PDT 24 Aug 09 07:16:13 PM PDT 24 185444584 ps
T117 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.1533832450 Aug 09 07:15:58 PM PDT 24 Aug 09 07:16:00 PM PDT 24 33835901 ps
T125 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.3337233421 Aug 09 07:15:51 PM PDT 24 Aug 09 07:15:55 PM PDT 24 908301745 ps
T553 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.1801070939 Aug 09 07:15:46 PM PDT 24 Aug 09 07:15:56 PM PDT 24 820738412 ps
T104 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.3883824813 Aug 09 07:16:01 PM PDT 24 Aug 09 07:16:09 PM PDT 24 599010654 ps
T128 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.3067890317 Aug 09 07:15:59 PM PDT 24 Aug 09 07:16:01 PM PDT 24 290626859 ps
T554 /workspace/coverage/cover_reg_top/45.hmac_intr_test.3262737114 Aug 09 07:16:04 PM PDT 24 Aug 09 07:16:05 PM PDT 24 13222785 ps
T555 /workspace/coverage/cover_reg_top/30.hmac_intr_test.631877457 Aug 09 07:16:07 PM PDT 24 Aug 09 07:16:08 PM PDT 24 10857973 ps
T556 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.2806674195 Aug 09 07:15:41 PM PDT 24 Aug 09 07:15:42 PM PDT 24 32438265 ps
T557 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.1644567213 Aug 09 07:15:46 PM PDT 24 Aug 09 07:15:47 PM PDT 24 67650511 ps
T558 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.2077899682 Aug 09 07:15:56 PM PDT 24 Aug 09 07:15:58 PM PDT 24 74013849 ps
T118 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.611154242 Aug 09 07:15:46 PM PDT 24 Aug 09 07:15:48 PM PDT 24 47171171 ps
T559 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.2029370897 Aug 09 07:15:43 PM PDT 24 Aug 09 07:15:49 PM PDT 24 783640954 ps
T126 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.1287683240 Aug 09 07:15:46 PM PDT 24 Aug 09 07:15:49 PM PDT 24 92072710 ps
T560 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.3342739522 Aug 09 07:15:50 PM PDT 24 Aug 09 07:17:08 PM PDT 24 18008253180 ps
T561 /workspace/coverage/cover_reg_top/17.hmac_intr_test.2546934838 Aug 09 07:15:54 PM PDT 24 Aug 09 07:15:55 PM PDT 24 14250936 ps
T562 /workspace/coverage/cover_reg_top/8.hmac_intr_test.3858825001 Aug 09 07:15:47 PM PDT 24 Aug 09 07:15:48 PM PDT 24 21874637 ps
T105 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.4147023773 Aug 09 07:15:59 PM PDT 24 Aug 09 07:16:00 PM PDT 24 31646285 ps
T563 /workspace/coverage/cover_reg_top/32.hmac_intr_test.1248807320 Aug 09 07:16:04 PM PDT 24 Aug 09 07:16:05 PM PDT 24 24024056 ps
T564 /workspace/coverage/cover_reg_top/36.hmac_intr_test.3511907978 Aug 09 07:16:04 PM PDT 24 Aug 09 07:16:04 PM PDT 24 42383828 ps
T106 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.2659958482 Aug 09 07:15:54 PM PDT 24 Aug 09 07:16:03 PM PDT 24 1190737817 ps
T119 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.3688774409 Aug 09 07:16:05 PM PDT 24 Aug 09 07:16:06 PM PDT 24 354755324 ps
T565 /workspace/coverage/cover_reg_top/5.hmac_intr_test.2544819388 Aug 09 07:15:47 PM PDT 24 Aug 09 07:15:47 PM PDT 24 20773551 ps
T107 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.3207099213 Aug 09 07:15:46 PM PDT 24 Aug 09 07:15:53 PM PDT 24 394825700 ps
T566 /workspace/coverage/cover_reg_top/26.hmac_intr_test.2434535446 Aug 09 07:16:03 PM PDT 24 Aug 09 07:16:04 PM PDT 24 45370161 ps
T120 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.3289590561 Aug 09 07:15:44 PM PDT 24 Aug 09 07:15:45 PM PDT 24 64739415 ps
T567 /workspace/coverage/cover_reg_top/34.hmac_intr_test.4287452545 Aug 09 07:15:57 PM PDT 24 Aug 09 07:15:58 PM PDT 24 51633526 ps
T568 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3578655414 Aug 09 07:15:53 PM PDT 24 Aug 09 07:15:54 PM PDT 24 21736071 ps
T569 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.276396988 Aug 09 07:15:51 PM PDT 24 Aug 09 07:15:52 PM PDT 24 85442415 ps
T570 /workspace/coverage/cover_reg_top/27.hmac_intr_test.2431686005 Aug 09 07:15:59 PM PDT 24 Aug 09 07:16:00 PM PDT 24 160536401 ps
T108 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.2235685376 Aug 09 07:15:50 PM PDT 24 Aug 09 07:15:51 PM PDT 24 61222774 ps
T571 /workspace/coverage/cover_reg_top/31.hmac_intr_test.3650021388 Aug 09 07:15:54 PM PDT 24 Aug 09 07:15:55 PM PDT 24 75558303 ps
T127 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.3384259518 Aug 09 07:16:06 PM PDT 24 Aug 09 07:16:08 PM PDT 24 320241511 ps
T572 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.3322328023 Aug 09 07:16:02 PM PDT 24 Aug 09 07:30:58 PM PDT 24 447413821881 ps
T573 /workspace/coverage/cover_reg_top/15.hmac_intr_test.1014180547 Aug 09 07:15:51 PM PDT 24 Aug 09 07:15:52 PM PDT 24 10886286 ps
T132 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2035807033 Aug 09 07:15:43 PM PDT 24 Aug 09 07:15:51 PM PDT 24 1506757599 ps
T574 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.3864839656 Aug 09 07:15:55 PM PDT 24 Aug 09 07:15:56 PM PDT 24 63819649 ps
T575 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.3400150214 Aug 09 07:16:03 PM PDT 24 Aug 09 07:16:04 PM PDT 24 28707772 ps
T576 /workspace/coverage/cover_reg_top/43.hmac_intr_test.3707131329 Aug 09 07:15:56 PM PDT 24 Aug 09 07:15:57 PM PDT 24 50477384 ps
T577 /workspace/coverage/cover_reg_top/47.hmac_intr_test.1808553309 Aug 09 07:15:59 PM PDT 24 Aug 09 07:16:00 PM PDT 24 15418788 ps
T578 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.3011906255 Aug 09 07:15:57 PM PDT 24 Aug 09 07:15:57 PM PDT 24 65420664 ps
T579 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.1500237575 Aug 09 07:15:44 PM PDT 24 Aug 09 07:15:45 PM PDT 24 42410931 ps
T109 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.2409380377 Aug 09 07:15:59 PM PDT 24 Aug 09 07:16:00 PM PDT 24 15797281 ps
T110 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.2413802538 Aug 09 07:15:46 PM PDT 24 Aug 09 07:15:47 PM PDT 24 122407955 ps
T111 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.3620497703 Aug 09 07:15:48 PM PDT 24 Aug 09 07:15:49 PM PDT 24 31628683 ps
T580 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1851700264 Aug 09 07:16:03 PM PDT 24 Aug 09 07:16:04 PM PDT 24 92477821 ps
T581 /workspace/coverage/cover_reg_top/2.hmac_intr_test.3812018861 Aug 09 07:15:44 PM PDT 24 Aug 09 07:15:45 PM PDT 24 56483927 ps
T112 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.3067552920 Aug 09 07:15:47 PM PDT 24 Aug 09 07:15:48 PM PDT 24 31486209 ps
T582 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.1007526726 Aug 09 07:15:46 PM PDT 24 Aug 09 07:15:48 PM PDT 24 262796939 ps
T583 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3209281640 Aug 09 07:15:44 PM PDT 24 Aug 09 07:15:46 PM PDT 24 23231494 ps
T129 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.806193205 Aug 09 07:15:51 PM PDT 24 Aug 09 07:15:53 PM PDT 24 180687527 ps
T584 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.506117734 Aug 09 07:15:43 PM PDT 24 Aug 09 07:15:45 PM PDT 24 64983143 ps
T585 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.4049581223 Aug 09 07:15:59 PM PDT 24 Aug 09 07:16:02 PM PDT 24 209872170 ps
T586 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.1976374111 Aug 09 07:15:46 PM PDT 24 Aug 09 07:15:47 PM PDT 24 15758383 ps
T587 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.3804629012 Aug 09 07:15:43 PM PDT 24 Aug 09 07:15:44 PM PDT 24 123823570 ps
T588 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.3684653908 Aug 09 07:15:58 PM PDT 24 Aug 09 07:16:03 PM PDT 24 279373917 ps
T589 /workspace/coverage/cover_reg_top/14.hmac_intr_test.1014501826 Aug 09 07:15:48 PM PDT 24 Aug 09 07:15:49 PM PDT 24 28129562 ps
T590 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.657102560 Aug 09 07:15:55 PM PDT 24 Aug 09 07:15:57 PM PDT 24 70705421 ps
T591 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.2668686598 Aug 09 07:15:59 PM PDT 24 Aug 09 07:16:02 PM PDT 24 484121407 ps
T592 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.3146686551 Aug 09 07:15:43 PM PDT 24 Aug 09 07:15:44 PM PDT 24 69651932 ps
T593 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.3178819215 Aug 09 07:15:43 PM PDT 24 Aug 09 07:15:46 PM PDT 24 320389405 ps
T130 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.614164601 Aug 09 07:15:47 PM PDT 24 Aug 09 07:15:50 PM PDT 24 296789798 ps
T594 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.3820025658 Aug 09 07:15:59 PM PDT 24 Aug 09 07:16:02 PM PDT 24 96752212 ps
T595 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.2371461381 Aug 09 07:15:45 PM PDT 24 Aug 09 07:15:48 PM PDT 24 39174917 ps
T596 /workspace/coverage/cover_reg_top/38.hmac_intr_test.3584472733 Aug 09 07:16:01 PM PDT 24 Aug 09 07:16:01 PM PDT 24 22878804 ps
T597 /workspace/coverage/cover_reg_top/20.hmac_intr_test.3916378663 Aug 09 07:15:51 PM PDT 24 Aug 09 07:15:52 PM PDT 24 25673650 ps
T598 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.3882880254 Aug 09 07:15:44 PM PDT 24 Aug 09 07:15:48 PM PDT 24 191814309 ps
T599 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.4012334922 Aug 09 07:16:05 PM PDT 24 Aug 09 07:16:07 PM PDT 24 48473596 ps
T600 /workspace/coverage/cover_reg_top/3.hmac_intr_test.1657728597 Aug 09 07:15:46 PM PDT 24 Aug 09 07:15:47 PM PDT 24 14435002 ps
T601 /workspace/coverage/cover_reg_top/4.hmac_intr_test.797796644 Aug 09 07:15:52 PM PDT 24 Aug 09 07:15:52 PM PDT 24 30477385 ps
T602 /workspace/coverage/cover_reg_top/24.hmac_intr_test.1068255062 Aug 09 07:16:00 PM PDT 24 Aug 09 07:16:01 PM PDT 24 165334294 ps
T603 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.527315732 Aug 09 07:15:59 PM PDT 24 Aug 09 07:16:01 PM PDT 24 189812530 ps
T604 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.2308605893 Aug 09 07:15:53 PM PDT 24 Aug 09 07:15:55 PM PDT 24 281898013 ps
T605 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.606569402 Aug 09 07:15:50 PM PDT 24 Aug 09 07:15:52 PM PDT 24 114664511 ps
T606 /workspace/coverage/cover_reg_top/28.hmac_intr_test.1509533998 Aug 09 07:16:03 PM PDT 24 Aug 09 07:16:04 PM PDT 24 47893858 ps
T607 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.2786717955 Aug 09 07:15:47 PM PDT 24 Aug 09 07:15:49 PM PDT 24 103087956 ps
T608 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.2951786069 Aug 09 07:15:51 PM PDT 24 Aug 09 07:15:52 PM PDT 24 49889224 ps
T609 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.511795790 Aug 09 07:15:59 PM PDT 24 Aug 09 07:16:00 PM PDT 24 69066625 ps
T610 /workspace/coverage/cover_reg_top/41.hmac_intr_test.2202874193 Aug 09 07:16:04 PM PDT 24 Aug 09 07:16:04 PM PDT 24 43757828 ps
T611 /workspace/coverage/cover_reg_top/9.hmac_intr_test.147750102 Aug 09 07:15:44 PM PDT 24 Aug 09 07:15:44 PM PDT 24 42941433 ps
T612 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.286538407 Aug 09 07:16:00 PM PDT 24 Aug 09 07:16:01 PM PDT 24 105090566 ps
T613 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2695807199 Aug 09 07:15:46 PM PDT 24 Aug 09 07:15:48 PM PDT 24 139345603 ps
T614 /workspace/coverage/cover_reg_top/6.hmac_intr_test.3703923205 Aug 09 07:15:43 PM PDT 24 Aug 09 07:15:43 PM PDT 24 26888730 ps
T615 /workspace/coverage/cover_reg_top/12.hmac_intr_test.3923714780 Aug 09 07:15:45 PM PDT 24 Aug 09 07:15:46 PM PDT 24 63157000 ps
T616 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.3785073290 Aug 09 07:15:48 PM PDT 24 Aug 09 07:15:50 PM PDT 24 99601755 ps
T617 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.3504122837 Aug 09 07:15:56 PM PDT 24 Aug 09 07:28:33 PM PDT 24 51086925312 ps
T618 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.3937410756 Aug 09 07:15:48 PM PDT 24 Aug 09 07:15:49 PM PDT 24 47739430 ps
T619 /workspace/coverage/cover_reg_top/13.hmac_intr_test.924937751 Aug 09 07:15:47 PM PDT 24 Aug 09 07:15:48 PM PDT 24 21463612 ps
T620 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.3449776064 Aug 09 07:15:42 PM PDT 24 Aug 09 07:15:43 PM PDT 24 96427662 ps
T621 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.1850699532 Aug 09 07:15:55 PM PDT 24 Aug 09 07:15:56 PM PDT 24 13513681 ps
T622 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.797094729 Aug 09 07:15:59 PM PDT 24 Aug 09 07:16:01 PM PDT 24 76139046 ps
T133 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.937430155 Aug 09 07:16:00 PM PDT 24 Aug 09 07:16:05 PM PDT 24 1747818202 ps
T623 /workspace/coverage/cover_reg_top/44.hmac_intr_test.2439443176 Aug 09 07:15:59 PM PDT 24 Aug 09 07:16:00 PM PDT 24 48311734 ps
T624 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.2351148607 Aug 09 07:16:01 PM PDT 24 Aug 09 07:16:02 PM PDT 24 105929680 ps
T625 /workspace/coverage/cover_reg_top/16.hmac_intr_test.2983564111 Aug 09 07:16:03 PM PDT 24 Aug 09 07:16:04 PM PDT 24 11946489 ps
T626 /workspace/coverage/cover_reg_top/35.hmac_intr_test.33073915 Aug 09 07:16:02 PM PDT 24 Aug 09 07:16:03 PM PDT 24 34056472 ps
T627 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.1018314090 Aug 09 07:15:50 PM PDT 24 Aug 09 07:15:52 PM PDT 24 39141411 ps
T628 /workspace/coverage/cover_reg_top/39.hmac_intr_test.977598865 Aug 09 07:15:59 PM PDT 24 Aug 09 07:16:00 PM PDT 24 75455650 ps
T629 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.2299417703 Aug 09 07:15:53 PM PDT 24 Aug 09 07:15:58 PM PDT 24 468608827 ps
T630 /workspace/coverage/cover_reg_top/19.hmac_intr_test.2150476512 Aug 09 07:15:59 PM PDT 24 Aug 09 07:16:00 PM PDT 24 11681176 ps
T631 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.1088146326 Aug 09 07:15:49 PM PDT 24 Aug 09 07:15:51 PM PDT 24 193522144 ps
T131 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.360635405 Aug 09 07:15:59 PM PDT 24 Aug 09 07:16:01 PM PDT 24 205422837 ps
T632 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.4253712086 Aug 09 07:15:46 PM PDT 24 Aug 09 07:15:49 PM PDT 24 50603718 ps
T633 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.1553974220 Aug 09 07:16:02 PM PDT 24 Aug 09 07:16:06 PM PDT 24 1423945803 ps
T634 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.1053849398 Aug 09 07:15:44 PM PDT 24 Aug 09 07:15:45 PM PDT 24 27852798 ps
T635 /workspace/coverage/cover_reg_top/10.hmac_intr_test.4282094098 Aug 09 07:15:48 PM PDT 24 Aug 09 07:15:49 PM PDT 24 23612099 ps
T636 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.259932352 Aug 09 07:15:46 PM PDT 24 Aug 09 07:15:49 PM PDT 24 599518045 ps
T637 /workspace/coverage/cover_reg_top/40.hmac_intr_test.1337976544 Aug 09 07:15:54 PM PDT 24 Aug 09 07:15:55 PM PDT 24 111166829 ps
T638 /workspace/coverage/cover_reg_top/46.hmac_intr_test.949695238 Aug 09 07:16:04 PM PDT 24 Aug 09 07:16:04 PM PDT 24 30434077 ps
T639 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.2631109947 Aug 09 07:15:59 PM PDT 24 Aug 09 07:16:01 PM PDT 24 28717389 ps
T640 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2677843776 Aug 09 07:15:44 PM PDT 24 Aug 09 07:15:46 PM PDT 24 40973468 ps
T641 /workspace/coverage/cover_reg_top/49.hmac_intr_test.4123766687 Aug 09 07:15:59 PM PDT 24 Aug 09 07:16:00 PM PDT 24 52741390 ps
T642 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.1049948537 Aug 09 07:15:51 PM PDT 24 Aug 09 07:15:53 PM PDT 24 857727851 ps
T134 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.613412792 Aug 09 07:15:53 PM PDT 24 Aug 09 07:15:57 PM PDT 24 478080723 ps
T643 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3692025096 Aug 09 07:15:42 PM PDT 24 Aug 09 07:15:44 PM PDT 24 77415511 ps
T644 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.2346902457 Aug 09 07:15:44 PM PDT 24 Aug 09 07:15:45 PM PDT 24 104769551 ps
T645 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.3483346070 Aug 09 07:15:51 PM PDT 24 Aug 09 07:15:54 PM PDT 24 156486885 ps
T646 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.1433836882 Aug 09 07:15:44 PM PDT 24 Aug 09 07:15:46 PM PDT 24 386456958 ps
T647 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.793348692 Aug 09 07:15:52 PM PDT 24 Aug 09 07:15:56 PM PDT 24 180017804 ps
T648 /workspace/coverage/cover_reg_top/0.hmac_intr_test.2444678119 Aug 09 07:15:40 PM PDT 24 Aug 09 07:15:41 PM PDT 24 19544714 ps
T649 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.3151890115 Aug 09 07:15:58 PM PDT 24 Aug 09 07:15:59 PM PDT 24 261182736 ps
T650 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.959115834 Aug 09 07:16:00 PM PDT 24 Aug 09 07:16:02 PM PDT 24 238451461 ps
T651 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.3562555356 Aug 09 07:15:49 PM PDT 24 Aug 09 07:24:36 PM PDT 24 564104491946 ps
T652 /workspace/coverage/cover_reg_top/29.hmac_intr_test.2413301495 Aug 09 07:16:00 PM PDT 24 Aug 09 07:16:01 PM PDT 24 16431279 ps
T653 /workspace/coverage/cover_reg_top/7.hmac_intr_test.2627422263 Aug 09 07:16:01 PM PDT 24 Aug 09 07:16:02 PM PDT 24 13620243 ps
T654 /workspace/coverage/cover_reg_top/21.hmac_intr_test.1350942512 Aug 09 07:15:51 PM PDT 24 Aug 09 07:15:52 PM PDT 24 13510429 ps
T655 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.2656277380 Aug 09 07:15:44 PM PDT 24 Aug 09 07:15:46 PM PDT 24 343123089 ps
T656 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1410235724 Aug 09 07:15:59 PM PDT 24 Aug 09 07:16:02 PM PDT 24 194556873 ps
T657 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.3809500712 Aug 09 07:16:01 PM PDT 24 Aug 09 07:16:02 PM PDT 24 15530928 ps
T658 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.3527147882 Aug 09 07:16:06 PM PDT 24 Aug 09 07:16:09 PM PDT 24 158837648 ps
T659 /workspace/coverage/cover_reg_top/42.hmac_intr_test.3647713218 Aug 09 07:16:05 PM PDT 24 Aug 09 07:16:06 PM PDT 24 23217321 ps
T660 /workspace/coverage/cover_reg_top/1.hmac_intr_test.58041128 Aug 09 07:15:47 PM PDT 24 Aug 09 07:15:48 PM PDT 24 20815827 ps

Test location /workspace/coverage/default/24.hmac_datapath_stress.4180634168
Short name T4
Test name
Test status
Simulation time 10793866454 ps
CPU time 1439.36 seconds
Started Aug 09 07:16:38 PM PDT 24
Finished Aug 09 07:40:38 PM PDT 24
Peak memory 768180 kb
Host smart-a1d7175e-2e89-4d2e-a1d4-d23cc4ac90ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4180634168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.4180634168
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_stress_all_with_rand_reset.1723068306
Short name T11
Test name
Test status
Simulation time 64018702813 ps
CPU time 5009.43 seconds
Started Aug 09 07:16:05 PM PDT 24
Finished Aug 09 08:39:36 PM PDT 24
Peak memory 865264 kb
Host smart-fb389f0b-194e-4260-b763-c275b6c6f3f8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1723068306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all_with_rand_reset.1723068306
Directory /workspace/5.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.hmac_error.745166196
Short name T7
Test name
Test status
Simulation time 22118064418 ps
CPU time 179.46 seconds
Started Aug 09 07:16:23 PM PDT 24
Finished Aug 09 07:19:22 PM PDT 24
Peak memory 199848 kb
Host smart-4cae7a14-7e7a-43fd-bc6f-9f423df4b40b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745166196 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.745166196
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_stress_all.2917545326
Short name T8
Test name
Test status
Simulation time 17660342292 ps
CPU time 1389.44 seconds
Started Aug 09 07:16:12 PM PDT 24
Finished Aug 09 07:39:22 PM PDT 24
Peak memory 653404 kb
Host smart-53db7395-3fdd-4cf6-af48-7c4dbe607c8c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917545326 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.2917545326
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.830928991
Short name T66
Test name
Test status
Simulation time 89028242 ps
CPU time 2.73 seconds
Started Aug 09 07:16:03 PM PDT 24
Finished Aug 09 07:16:06 PM PDT 24
Peak memory 200092 kb
Host smart-aaf87565-84cb-4a55-93cc-1ce5b71806d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830928991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.830928991
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.1829995135
Short name T53
Test name
Test status
Simulation time 104815739 ps
CPU time 0.94 seconds
Started Aug 09 07:16:11 PM PDT 24
Finished Aug 09 07:16:12 PM PDT 24
Peak memory 219508 kb
Host smart-af37b316-45b2-46ae-a472-ababb9bcc666
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829995135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.1829995135
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.4119717505
Short name T101
Test name
Test status
Simulation time 23053965 ps
CPU time 0.67 seconds
Started Aug 09 07:15:51 PM PDT 24
Finished Aug 09 07:15:52 PM PDT 24
Peak memory 198272 kb
Host smart-6881a7b0-0b8e-4725-b953-47823be21cc3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119717505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.4119717505
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.110997102
Short name T19
Test name
Test status
Simulation time 3463745458 ps
CPU time 98.12 seconds
Started Aug 09 07:16:58 PM PDT 24
Finished Aug 09 07:18:36 PM PDT 24
Peak memory 199864 kb
Host smart-9379b766-5a24-4025-8f73-c06260f7b671
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=110997102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.110997102
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_stress_all.351680977
Short name T82
Test name
Test status
Simulation time 824962300520 ps
CPU time 7583.65 seconds
Started Aug 09 07:16:52 PM PDT 24
Finished Aug 09 09:23:16 PM PDT 24
Peak memory 904116 kb
Host smart-70dc186a-2776-4ac6-a353-44d1bc2ddcf4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351680977 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.351680977
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.937430155
Short name T133
Test name
Test status
Simulation time 1747818202 ps
CPU time 4.65 seconds
Started Aug 09 07:16:00 PM PDT 24
Finished Aug 09 07:16:05 PM PDT 24
Peak memory 200144 kb
Host smart-f2a2649c-dd7a-417d-af71-8e9bf74d64f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937430155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.937430155
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.87574314
Short name T172
Test name
Test status
Simulation time 11457792 ps
CPU time 0.59 seconds
Started Aug 09 07:16:02 PM PDT 24
Finished Aug 09 07:16:02 PM PDT 24
Peak memory 194928 kb
Host smart-e4275528-df7c-4051-81f4-f3d64491901b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87574314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.87574314
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_stress_all.1358372581
Short name T27
Test name
Test status
Simulation time 159056792424 ps
CPU time 2122.2 seconds
Started Aug 09 07:16:51 PM PDT 24
Finished Aug 09 07:52:14 PM PDT 24
Peak memory 796144 kb
Host smart-4c7eabf1-7939-4cbd-a785-7ff668b85e00
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358372581 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.1358372581
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.1517231703
Short name T137
Test name
Test status
Simulation time 2813299778 ps
CPU time 63.74 seconds
Started Aug 09 07:16:59 PM PDT 24
Finished Aug 09 07:18:02 PM PDT 24
Peak memory 199924 kb
Host smart-e2db0f9b-f6da-40bd-81d4-d73623cf504a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1517231703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.1517231703
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.360635405
Short name T131
Test name
Test status
Simulation time 205422837 ps
CPU time 2.02 seconds
Started Aug 09 07:15:59 PM PDT 24
Finished Aug 09 07:16:01 PM PDT 24
Peak memory 200108 kb
Host smart-74c2e7f5-6aa3-4e0a-89cc-85a8d8e97ec0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360635405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.360635405
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/3.hmac_stress_all_with_rand_reset.3594957400
Short name T21
Test name
Test status
Simulation time 72373957720 ps
CPU time 1737.19 seconds
Started Aug 09 07:16:19 PM PDT 24
Finished Aug 09 07:45:17 PM PDT 24
Peak memory 698600 kb
Host smart-90c7b225-0033-43fe-9b85-7c6dfc79a96e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3594957400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all_with_rand_reset.3594957400
Directory /workspace/3.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.2659958482
Short name T106
Test name
Test status
Simulation time 1190737817 ps
CPU time 9.14 seconds
Started Aug 09 07:15:54 PM PDT 24
Finished Aug 09 07:16:03 PM PDT 24
Peak memory 200092 kb
Host smart-1d36ba52-c719-43ed-baaf-78e2678d5fcf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659958482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.2659958482
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.1651146618
Short name T551
Test name
Test status
Simulation time 736175217 ps
CPU time 10.86 seconds
Started Aug 09 07:15:47 PM PDT 24
Finished Aug 09 07:15:58 PM PDT 24
Peak memory 200152 kb
Host smart-c47c7632-afb9-49ad-9011-e55533bf8fcc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651146618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.1651146618
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.1500237575
Short name T579
Test name
Test status
Simulation time 42410931 ps
CPU time 0.99 seconds
Started Aug 09 07:15:44 PM PDT 24
Finished Aug 09 07:15:45 PM PDT 24
Peak memory 199640 kb
Host smart-9f4a5930-b7c9-46fc-8ac9-e326f1150f9c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500237575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.1500237575
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2677843776
Short name T640
Test name
Test status
Simulation time 40973468 ps
CPU time 2.44 seconds
Started Aug 09 07:15:44 PM PDT 24
Finished Aug 09 07:15:46 PM PDT 24
Peak memory 200320 kb
Host smart-4b5d3282-5cda-4e11-86ad-53382ce2e233
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677843776 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.2677843776
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.2631109947
Short name T639
Test name
Test status
Simulation time 28717389 ps
CPU time 0.85 seconds
Started Aug 09 07:15:59 PM PDT 24
Finished Aug 09 07:16:01 PM PDT 24
Peak memory 199872 kb
Host smart-61be305c-782b-4987-a6c6-13cdf74a8ec9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631109947 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.2631109947
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.2444678119
Short name T648
Test name
Test status
Simulation time 19544714 ps
CPU time 0.61 seconds
Started Aug 09 07:15:40 PM PDT 24
Finished Aug 09 07:15:41 PM PDT 24
Peak memory 195024 kb
Host smart-4e198006-7c81-4915-be77-8bdc5f297c0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444678119 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.2444678119
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3209281640
Short name T583
Test name
Test status
Simulation time 23231494 ps
CPU time 1.14 seconds
Started Aug 09 07:15:44 PM PDT 24
Finished Aug 09 07:15:46 PM PDT 24
Peak memory 198692 kb
Host smart-97baf965-c745-4c43-91b6-6ded861822b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209281640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.3209281640
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.1007526726
Short name T582
Test name
Test status
Simulation time 262796939 ps
CPU time 2.4 seconds
Started Aug 09 07:15:46 PM PDT 24
Finished Aug 09 07:15:48 PM PDT 24
Peak memory 200152 kb
Host smart-0c3b9382-3e35-4dfb-ab78-122c07cc7cae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007526726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.1007526726
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2035807033
Short name T132
Test name
Test status
Simulation time 1506757599 ps
CPU time 3.08 seconds
Started Aug 09 07:15:43 PM PDT 24
Finished Aug 09 07:15:51 PM PDT 24
Peak memory 200196 kb
Host smart-c10a805d-8ad6-4b18-9759-e935672928dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035807033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.2035807033
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.3207099213
Short name T107
Test name
Test status
Simulation time 394825700 ps
CPU time 6.52 seconds
Started Aug 09 07:15:46 PM PDT 24
Finished Aug 09 07:15:53 PM PDT 24
Peak memory 200144 kb
Host smart-251984db-8a03-4b8c-9a70-5ce139f1ee1c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207099213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.3207099213
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.2029370897
Short name T559
Test name
Test status
Simulation time 783640954 ps
CPU time 5.89 seconds
Started Aug 09 07:15:43 PM PDT 24
Finished Aug 09 07:15:49 PM PDT 24
Peak memory 200100 kb
Host smart-6454990b-9075-459c-9f89-d813c480935b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029370897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.2029370897
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.3067552920
Short name T112
Test name
Test status
Simulation time 31486209 ps
CPU time 0.87 seconds
Started Aug 09 07:15:47 PM PDT 24
Finished Aug 09 07:15:48 PM PDT 24
Peak memory 199692 kb
Host smart-48baf890-091f-4af5-846b-44ac5f0df93c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067552920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.3067552920
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2695807199
Short name T613
Test name
Test status
Simulation time 139345603 ps
CPU time 1.78 seconds
Started Aug 09 07:15:46 PM PDT 24
Finished Aug 09 07:15:48 PM PDT 24
Peak memory 200116 kb
Host smart-5f02eef3-3125-4706-8d98-6a95f760f3e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695807199 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.2695807199
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.286538407
Short name T612
Test name
Test status
Simulation time 105090566 ps
CPU time 0.93 seconds
Started Aug 09 07:16:00 PM PDT 24
Finished Aug 09 07:16:01 PM PDT 24
Peak memory 199652 kb
Host smart-8b2cc8fa-9d55-457d-bb45-d9b17e37b47d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286538407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.286538407
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.58041128
Short name T660
Test name
Test status
Simulation time 20815827 ps
CPU time 0.58 seconds
Started Aug 09 07:15:47 PM PDT 24
Finished Aug 09 07:15:48 PM PDT 24
Peak memory 195000 kb
Host smart-b576e201-2c31-4fbe-9662-4f732086cb10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58041128 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.58041128
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.119140999
Short name T113
Test name
Test status
Simulation time 107033369 ps
CPU time 1.82 seconds
Started Aug 09 07:15:53 PM PDT 24
Finished Aug 09 07:15:55 PM PDT 24
Peak memory 200088 kb
Host smart-0981d938-f7ac-47e3-b472-f47bdfe5ae66
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119140999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr_
outstanding.119140999
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.3804629012
Short name T587
Test name
Test status
Simulation time 123823570 ps
CPU time 1.49 seconds
Started Aug 09 07:15:43 PM PDT 24
Finished Aug 09 07:15:44 PM PDT 24
Peak memory 200120 kb
Host smart-c3b421ec-2210-42cc-9d65-a09565341706
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804629012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.3804629012
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.3562555356
Short name T651
Test name
Test status
Simulation time 564104491946 ps
CPU time 527.11 seconds
Started Aug 09 07:15:49 PM PDT 24
Finished Aug 09 07:24:36 PM PDT 24
Peak memory 216640 kb
Host smart-2f54d2d8-bc06-4ef6-8a31-a101f20092ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562555356 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.3562555356
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.2413802538
Short name T110
Test name
Test status
Simulation time 122407955 ps
CPU time 0.93 seconds
Started Aug 09 07:15:46 PM PDT 24
Finished Aug 09 07:15:47 PM PDT 24
Peak memory 199280 kb
Host smart-545b3e0a-a872-478f-9a6e-e95ab09debd1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413802538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.2413802538
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.4282094098
Short name T635
Test name
Test status
Simulation time 23612099 ps
CPU time 0.6 seconds
Started Aug 09 07:15:48 PM PDT 24
Finished Aug 09 07:15:49 PM PDT 24
Peak memory 195024 kb
Host smart-cdbf584d-b533-41a8-904a-9d5ddbad2352
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282094098 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.4282094098
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.2850213828
Short name T116
Test name
Test status
Simulation time 113669113 ps
CPU time 2.31 seconds
Started Aug 09 07:16:03 PM PDT 24
Finished Aug 09 07:16:05 PM PDT 24
Peak memory 200112 kb
Host smart-5aca06ba-dd5a-465e-8813-467b788dfb27
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850213828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.2850213828
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.259932352
Short name T636
Test name
Test status
Simulation time 599518045 ps
CPU time 2.93 seconds
Started Aug 09 07:15:46 PM PDT 24
Finished Aug 09 07:15:49 PM PDT 24
Peak memory 200128 kb
Host smart-a6e8dbb1-c2d0-4ac1-b610-09ada82f929a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259932352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.259932352
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.2299417703
Short name T629
Test name
Test status
Simulation time 468608827 ps
CPU time 4.08 seconds
Started Aug 09 07:15:53 PM PDT 24
Finished Aug 09 07:15:58 PM PDT 24
Peak memory 200372 kb
Host smart-1434eb0b-176d-491c-a5fa-efa61f071b82
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299417703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.2299417703
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.594405691
Short name T545
Test name
Test status
Simulation time 48194303871 ps
CPU time 240.99 seconds
Started Aug 09 07:15:57 PM PDT 24
Finished Aug 09 07:19:58 PM PDT 24
Peak memory 216612 kb
Host smart-239fa777-86e5-4bee-ae85-7fbe8233bb08
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594405691 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.594405691
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.3449776064
Short name T620
Test name
Test status
Simulation time 96427662 ps
CPU time 0.68 seconds
Started Aug 09 07:15:42 PM PDT 24
Finished Aug 09 07:15:43 PM PDT 24
Peak memory 198100 kb
Host smart-e4ba4df8-612a-46a8-a08d-177494f3348b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449776064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.3449776064
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.59086602
Short name T543
Test name
Test status
Simulation time 25873805 ps
CPU time 0.6 seconds
Started Aug 09 07:16:03 PM PDT 24
Finished Aug 09 07:16:04 PM PDT 24
Peak memory 195232 kb
Host smart-28e6b120-b7fa-450f-8b16-9b5b11dd0872
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59086602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.59086602
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.606569402
Short name T605
Test name
Test status
Simulation time 114664511 ps
CPU time 2.48 seconds
Started Aug 09 07:15:50 PM PDT 24
Finished Aug 09 07:15:52 PM PDT 24
Peak memory 200132 kb
Host smart-a01c3421-510b-4147-a660-5f3edc9e84f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606569402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_csr
_outstanding.606569402
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.3214188517
Short name T536
Test name
Test status
Simulation time 459479987 ps
CPU time 1.38 seconds
Started Aug 09 07:15:43 PM PDT 24
Finished Aug 09 07:15:44 PM PDT 24
Peak memory 200128 kb
Host smart-1d117213-85e8-4cfb-90b5-929143351894
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214188517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.3214188517
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1410235724
Short name T656
Test name
Test status
Simulation time 194556873 ps
CPU time 2.28 seconds
Started Aug 09 07:15:59 PM PDT 24
Finished Aug 09 07:16:02 PM PDT 24
Peak memory 200396 kb
Host smart-592920b1-118a-43df-83a0-c6250ddc9722
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410235724 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.1410235724
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.2235685376
Short name T108
Test name
Test status
Simulation time 61222774 ps
CPU time 0.9 seconds
Started Aug 09 07:15:50 PM PDT 24
Finished Aug 09 07:15:51 PM PDT 24
Peak memory 199792 kb
Host smart-5aace0a1-2101-4ae2-befc-761c33dd20e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235685376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.2235685376
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.3923714780
Short name T615
Test name
Test status
Simulation time 63157000 ps
CPU time 0.57 seconds
Started Aug 09 07:15:45 PM PDT 24
Finished Aug 09 07:15:46 PM PDT 24
Peak memory 195128 kb
Host smart-03c26ea0-cfec-4845-b93d-31012e455a4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923714780 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.3923714780
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.506117734
Short name T584
Test name
Test status
Simulation time 64983143 ps
CPU time 1.57 seconds
Started Aug 09 07:15:43 PM PDT 24
Finished Aug 09 07:15:45 PM PDT 24
Peak memory 199932 kb
Host smart-296dc38b-e173-4bed-8e95-e8c8811f0d96
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506117734 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_csr
_outstanding.506117734
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.657102560
Short name T590
Test name
Test status
Simulation time 70705421 ps
CPU time 1.76 seconds
Started Aug 09 07:15:55 PM PDT 24
Finished Aug 09 07:15:57 PM PDT 24
Peak memory 200112 kb
Host smart-30ee150d-3f55-4331-aebb-beac6830948c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657102560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.657102560
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.614164601
Short name T130
Test name
Test status
Simulation time 296789798 ps
CPU time 3.3 seconds
Started Aug 09 07:15:47 PM PDT 24
Finished Aug 09 07:15:50 PM PDT 24
Peak memory 200404 kb
Host smart-15988d21-f0d5-495f-9522-518d257d1ce1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614164601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.614164601
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.3504122837
Short name T617
Test name
Test status
Simulation time 51086925312 ps
CPU time 757.24 seconds
Started Aug 09 07:15:56 PM PDT 24
Finished Aug 09 07:28:33 PM PDT 24
Peak memory 216548 kb
Host smart-80723e11-a846-40a8-a4d1-83424cca8dce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504122837 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.3504122837
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.3640239772
Short name T100
Test name
Test status
Simulation time 31937103 ps
CPU time 0.98 seconds
Started Aug 09 07:15:50 PM PDT 24
Finished Aug 09 07:15:51 PM PDT 24
Peak memory 199932 kb
Host smart-88fc6245-01a8-456d-8bf3-c7014069af8f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640239772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.3640239772
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.924937751
Short name T619
Test name
Test status
Simulation time 21463612 ps
CPU time 0.59 seconds
Started Aug 09 07:15:47 PM PDT 24
Finished Aug 09 07:15:48 PM PDT 24
Peak memory 195140 kb
Host smart-0cfaee93-e64a-4ea3-8004-f35b5b3ce9c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924937751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.924937751
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.3688774409
Short name T119
Test name
Test status
Simulation time 354755324 ps
CPU time 1.16 seconds
Started Aug 09 07:16:05 PM PDT 24
Finished Aug 09 07:16:06 PM PDT 24
Peak memory 200196 kb
Host smart-f929407a-0e5b-439f-af9d-266fea584d29
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688774409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.3688774409
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.2951786069
Short name T608
Test name
Test status
Simulation time 49889224 ps
CPU time 1.34 seconds
Started Aug 09 07:15:51 PM PDT 24
Finished Aug 09 07:15:52 PM PDT 24
Peak memory 200172 kb
Host smart-9c448565-0d0c-4fb5-ae90-0999fb1b7069
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951786069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.2951786069
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.3337233421
Short name T125
Test name
Test status
Simulation time 908301745 ps
CPU time 3.93 seconds
Started Aug 09 07:15:51 PM PDT 24
Finished Aug 09 07:15:55 PM PDT 24
Peak memory 200148 kb
Host smart-4ab049ef-150b-40b7-8762-71854bbba8c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337233421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.3337233421
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.3527147882
Short name T658
Test name
Test status
Simulation time 158837648 ps
CPU time 2.86 seconds
Started Aug 09 07:16:06 PM PDT 24
Finished Aug 09 07:16:09 PM PDT 24
Peak memory 208376 kb
Host smart-be4f38f3-afe9-43e2-bafa-1007dfb0ec76
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527147882 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.3527147882
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.2409380377
Short name T109
Test name
Test status
Simulation time 15797281 ps
CPU time 0.81 seconds
Started Aug 09 07:15:59 PM PDT 24
Finished Aug 09 07:16:00 PM PDT 24
Peak memory 199960 kb
Host smart-4ce439f1-15f5-4d9a-bd67-f0e86abee8d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409380377 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.2409380377
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.1014501826
Short name T589
Test name
Test status
Simulation time 28129562 ps
CPU time 0.63 seconds
Started Aug 09 07:15:48 PM PDT 24
Finished Aug 09 07:15:49 PM PDT 24
Peak memory 195056 kb
Host smart-6e9b71be-974b-4895-9922-8564f45db8e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014501826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.1014501826
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.2668686598
Short name T591
Test name
Test status
Simulation time 484121407 ps
CPU time 2.48 seconds
Started Aug 09 07:15:59 PM PDT 24
Finished Aug 09 07:16:02 PM PDT 24
Peak memory 199944 kb
Host smart-1e86610e-c706-4eba-888b-bc38fdeac343
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668686598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.2668686598
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.793348692
Short name T647
Test name
Test status
Simulation time 180017804 ps
CPU time 3.77 seconds
Started Aug 09 07:15:52 PM PDT 24
Finished Aug 09 07:15:56 PM PDT 24
Peak memory 200076 kb
Host smart-2d2f9ca2-b3d9-4c00-8fae-956d97733ea0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793348692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.793348692
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.1088146326
Short name T631
Test name
Test status
Simulation time 193522144 ps
CPU time 1.93 seconds
Started Aug 09 07:15:49 PM PDT 24
Finished Aug 09 07:15:51 PM PDT 24
Peak memory 200076 kb
Host smart-e6812bce-4b40-4748-9947-fbf5ebef0a6a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088146326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.1088146326
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.3785073290
Short name T616
Test name
Test status
Simulation time 99601755 ps
CPU time 1.78 seconds
Started Aug 09 07:15:48 PM PDT 24
Finished Aug 09 07:15:50 PM PDT 24
Peak memory 200092 kb
Host smart-adb13bc8-2657-4c67-86aa-f89427c83036
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785073290 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.3785073290
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.3011906255
Short name T578
Test name
Test status
Simulation time 65420664 ps
CPU time 0.7 seconds
Started Aug 09 07:15:57 PM PDT 24
Finished Aug 09 07:15:57 PM PDT 24
Peak memory 197720 kb
Host smart-2837a2e6-b1c8-415b-a48f-7a9d434d5ed0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011906255 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.3011906255
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.1014180547
Short name T573
Test name
Test status
Simulation time 10886286 ps
CPU time 0.62 seconds
Started Aug 09 07:15:51 PM PDT 24
Finished Aug 09 07:15:52 PM PDT 24
Peak memory 195048 kb
Host smart-a59e82d6-1dd4-4261-9e5f-2c188354ed6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014180547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.1014180547
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.511795790
Short name T609
Test name
Test status
Simulation time 69066625 ps
CPU time 1.11 seconds
Started Aug 09 07:15:59 PM PDT 24
Finished Aug 09 07:16:00 PM PDT 24
Peak memory 199940 kb
Host smart-ac5c91c3-b3ca-4a78-a26e-88a8dba83b91
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511795790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_csr
_outstanding.511795790
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.1553974220
Short name T633
Test name
Test status
Simulation time 1423945803 ps
CPU time 3.15 seconds
Started Aug 09 07:16:02 PM PDT 24
Finished Aug 09 07:16:06 PM PDT 24
Peak memory 200112 kb
Host smart-569635f8-22c8-4695-90de-e0de4c30ed27
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553974220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.1553974220
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.2393490714
Short name T68
Test name
Test status
Simulation time 167275915 ps
CPU time 1.74 seconds
Started Aug 09 07:15:51 PM PDT 24
Finished Aug 09 07:15:53 PM PDT 24
Peak memory 200156 kb
Host smart-f8d9231d-d56e-4cfe-9a92-7928825caf7b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393490714 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.2393490714
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.4125045602
Short name T537
Test name
Test status
Simulation time 92701320774 ps
CPU time 909.43 seconds
Started Aug 09 07:16:05 PM PDT 24
Finished Aug 09 07:31:14 PM PDT 24
Peak memory 216608 kb
Host smart-20b84e87-1480-40b6-a15f-bb9db3dccec6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125045602 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.4125045602
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.3151890115
Short name T649
Test name
Test status
Simulation time 261182736 ps
CPU time 0.96 seconds
Started Aug 09 07:15:58 PM PDT 24
Finished Aug 09 07:15:59 PM PDT 24
Peak memory 199656 kb
Host smart-6aa44b3f-4dba-4eb3-9c14-c69f27eaabac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151890115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.3151890115
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.2983564111
Short name T625
Test name
Test status
Simulation time 11946489 ps
CPU time 0.6 seconds
Started Aug 09 07:16:03 PM PDT 24
Finished Aug 09 07:16:04 PM PDT 24
Peak memory 195008 kb
Host smart-612fc223-afa0-476a-b614-a67d68109625
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983564111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.2983564111
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1851700264
Short name T580
Test name
Test status
Simulation time 92477821 ps
CPU time 1.13 seconds
Started Aug 09 07:16:03 PM PDT 24
Finished Aug 09 07:16:04 PM PDT 24
Peak memory 198700 kb
Host smart-172a8c9c-f8aa-4032-b02e-2b3edcf62b00
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851700264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.1851700264
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.3417133313
Short name T539
Test name
Test status
Simulation time 475476605 ps
CPU time 1.2 seconds
Started Aug 09 07:15:58 PM PDT 24
Finished Aug 09 07:16:00 PM PDT 24
Peak memory 200136 kb
Host smart-bf7b67c5-cc92-44f5-a2e5-5cef78463908
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417133313 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.3417133313
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.527315732
Short name T603
Test name
Test status
Simulation time 189812530 ps
CPU time 1.82 seconds
Started Aug 09 07:15:59 PM PDT 24
Finished Aug 09 07:16:01 PM PDT 24
Peak memory 200116 kb
Host smart-8bfc4dcf-d57c-4d69-bd33-2a128910bd37
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527315732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.527315732
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.2063834565
Short name T548
Test name
Test status
Simulation time 316773397 ps
CPU time 2.2 seconds
Started Aug 09 07:16:04 PM PDT 24
Finished Aug 09 07:16:06 PM PDT 24
Peak memory 200128 kb
Host smart-41c70b4c-361e-43ae-b2f8-713f65017224
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063834565 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.2063834565
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.3937410756
Short name T618
Test name
Test status
Simulation time 47739430 ps
CPU time 0.84 seconds
Started Aug 09 07:15:48 PM PDT 24
Finished Aug 09 07:15:49 PM PDT 24
Peak memory 199460 kb
Host smart-8202f308-35b3-4983-95bf-e8f135fa8223
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937410756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.3937410756
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.2546934838
Short name T561
Test name
Test status
Simulation time 14250936 ps
CPU time 0.6 seconds
Started Aug 09 07:15:54 PM PDT 24
Finished Aug 09 07:15:55 PM PDT 24
Peak memory 195096 kb
Host smart-27dae9c3-5f02-4ac2-81bb-056d82f184ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546934838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.2546934838
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.3864839656
Short name T574
Test name
Test status
Simulation time 63819649 ps
CPU time 1.63 seconds
Started Aug 09 07:15:55 PM PDT 24
Finished Aug 09 07:15:56 PM PDT 24
Peak memory 200124 kb
Host smart-79997e37-5c7b-40e3-a9b1-ab674878de8d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864839656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.3864839656
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.797094729
Short name T622
Test name
Test status
Simulation time 76139046 ps
CPU time 1.87 seconds
Started Aug 09 07:15:59 PM PDT 24
Finished Aug 09 07:16:01 PM PDT 24
Peak memory 200356 kb
Host smart-72fe1529-9d88-4518-bc11-bde6cbc9f355
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797094729 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.797094729
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.3384259518
Short name T127
Test name
Test status
Simulation time 320241511 ps
CPU time 2.05 seconds
Started Aug 09 07:16:06 PM PDT 24
Finished Aug 09 07:16:08 PM PDT 24
Peak memory 200200 kb
Host smart-0d5e1bd7-617d-460d-a28e-b5828097e6c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384259518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.3384259518
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.2077899682
Short name T558
Test name
Test status
Simulation time 74013849 ps
CPU time 2.14 seconds
Started Aug 09 07:15:56 PM PDT 24
Finished Aug 09 07:15:58 PM PDT 24
Peak memory 200192 kb
Host smart-a7f456ee-0f8b-4612-a7d6-86e84f5bfc83
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077899682 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.2077899682
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.3809500712
Short name T657
Test name
Test status
Simulation time 15530928 ps
CPU time 0.82 seconds
Started Aug 09 07:16:01 PM PDT 24
Finished Aug 09 07:16:02 PM PDT 24
Peak memory 199908 kb
Host smart-1fffb6ed-ac17-49eb-918a-0cfea8eefb35
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809500712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.3809500712
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.394124741
Short name T544
Test name
Test status
Simulation time 42145592 ps
CPU time 0.63 seconds
Started Aug 09 07:16:00 PM PDT 24
Finished Aug 09 07:16:00 PM PDT 24
Peak memory 194976 kb
Host smart-dace1f60-02fa-4517-8b07-da1d6b04b13a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394124741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.394124741
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.679497902
Short name T115
Test name
Test status
Simulation time 185358186 ps
CPU time 1.75 seconds
Started Aug 09 07:15:59 PM PDT 24
Finished Aug 09 07:16:01 PM PDT 24
Peak memory 200092 kb
Host smart-976a19eb-5f6e-41b5-be48-0450f5644a1d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679497902 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_csr
_outstanding.679497902
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.302941422
Short name T540
Test name
Test status
Simulation time 730795119 ps
CPU time 2.83 seconds
Started Aug 09 07:16:03 PM PDT 24
Finished Aug 09 07:16:06 PM PDT 24
Peak memory 200084 kb
Host smart-be546448-066d-454d-920c-c373273a85bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302941422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.302941422
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.2288321799
Short name T532
Test name
Test status
Simulation time 87681855 ps
CPU time 2.37 seconds
Started Aug 09 07:16:03 PM PDT 24
Finished Aug 09 07:16:05 PM PDT 24
Peak memory 200076 kb
Host smart-6c59fd1d-1f7e-43e6-a483-a871c282d7fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288321799 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.2288321799
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.4147023773
Short name T105
Test name
Test status
Simulation time 31646285 ps
CPU time 0.7 seconds
Started Aug 09 07:15:59 PM PDT 24
Finished Aug 09 07:16:00 PM PDT 24
Peak memory 198248 kb
Host smart-679eea54-4a1c-4cc3-8d3a-000cb1b6bbda
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147023773 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.4147023773
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.2150476512
Short name T630
Test name
Test status
Simulation time 11681176 ps
CPU time 0.6 seconds
Started Aug 09 07:15:59 PM PDT 24
Finished Aug 09 07:16:00 PM PDT 24
Peak memory 195012 kb
Host smart-a7bd8c89-9048-46a1-b35d-2315f6eb4ca8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150476512 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.2150476512
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.4012334922
Short name T599
Test name
Test status
Simulation time 48473596 ps
CPU time 2.19 seconds
Started Aug 09 07:16:05 PM PDT 24
Finished Aug 09 07:16:07 PM PDT 24
Peak memory 200136 kb
Host smart-c62a21f8-e426-4bf9-b3ce-8f2e4f1b31d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012334922 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.4012334922
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.2249899755
Short name T552
Test name
Test status
Simulation time 185444584 ps
CPU time 3.35 seconds
Started Aug 09 07:16:10 PM PDT 24
Finished Aug 09 07:16:13 PM PDT 24
Peak memory 200144 kb
Host smart-df22713d-d19a-45fb-9f2f-36488f6a83d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249899755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.2249899755
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.613412792
Short name T134
Test name
Test status
Simulation time 478080723 ps
CPU time 4.4 seconds
Started Aug 09 07:15:53 PM PDT 24
Finished Aug 09 07:15:57 PM PDT 24
Peak memory 200108 kb
Host smart-6cb6cc82-cfb4-45c3-bda4-7bc99c5894f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613412792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.613412792
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.49953464
Short name T99
Test name
Test status
Simulation time 612545901 ps
CPU time 7.71 seconds
Started Aug 09 07:15:46 PM PDT 24
Finished Aug 09 07:15:54 PM PDT 24
Peak memory 199936 kb
Host smart-989ce2eb-ec06-472c-b80b-fd192400099b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49953464 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.49953464
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.1801070939
Short name T553
Test name
Test status
Simulation time 820738412 ps
CPU time 9.72 seconds
Started Aug 09 07:15:46 PM PDT 24
Finished Aug 09 07:15:56 PM PDT 24
Peak memory 200096 kb
Host smart-37fe0f8a-154c-4dc0-8081-67764759fd9e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801070939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.1801070939
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.1976374111
Short name T586
Test name
Test status
Simulation time 15758383 ps
CPU time 0.72 seconds
Started Aug 09 07:15:46 PM PDT 24
Finished Aug 09 07:15:47 PM PDT 24
Peak memory 197708 kb
Host smart-2fd313f7-fe5e-4950-9902-a6c5eaf3b9dc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976374111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.1976374111
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.2819540838
Short name T535
Test name
Test status
Simulation time 96770414 ps
CPU time 2.31 seconds
Started Aug 09 07:15:48 PM PDT 24
Finished Aug 09 07:15:51 PM PDT 24
Peak memory 200188 kb
Host smart-db017a32-4202-48e8-a0fc-6b2b1881980a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819540838 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.2819540838
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.1644567213
Short name T557
Test name
Test status
Simulation time 67650511 ps
CPU time 0.7 seconds
Started Aug 09 07:15:46 PM PDT 24
Finished Aug 09 07:15:47 PM PDT 24
Peak memory 197656 kb
Host smart-ee3e5602-8f11-4097-b0ce-c494fac8a30e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644567213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.1644567213
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.3812018861
Short name T581
Test name
Test status
Simulation time 56483927 ps
CPU time 0.57 seconds
Started Aug 09 07:15:44 PM PDT 24
Finished Aug 09 07:15:45 PM PDT 24
Peak memory 194968 kb
Host smart-37151c8c-c035-402f-bf5c-da4aec991587
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812018861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.3812018861
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.2308605893
Short name T604
Test name
Test status
Simulation time 281898013 ps
CPU time 2.34 seconds
Started Aug 09 07:15:53 PM PDT 24
Finished Aug 09 07:15:55 PM PDT 24
Peak memory 200144 kb
Host smart-3af5aae0-2a0e-43f7-8e60-31cee34804b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308605893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.2308605893
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.3684653908
Short name T588
Test name
Test status
Simulation time 279373917 ps
CPU time 4.16 seconds
Started Aug 09 07:15:58 PM PDT 24
Finished Aug 09 07:16:03 PM PDT 24
Peak memory 200056 kb
Host smart-5982e129-6038-4b65-a437-74ce7ecb577c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684653908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.3684653908
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.3067890317
Short name T128
Test name
Test status
Simulation time 290626859 ps
CPU time 1.77 seconds
Started Aug 09 07:15:59 PM PDT 24
Finished Aug 09 07:16:01 PM PDT 24
Peak memory 200100 kb
Host smart-64b76c5e-a764-4d93-ac9d-e3e35dabcf94
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067890317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.3067890317
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.3916378663
Short name T597
Test name
Test status
Simulation time 25673650 ps
CPU time 0.62 seconds
Started Aug 09 07:15:51 PM PDT 24
Finished Aug 09 07:15:52 PM PDT 24
Peak memory 195052 kb
Host smart-81af9ff0-cd2e-45c8-be33-66b77c6effd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916378663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.3916378663
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.1350942512
Short name T654
Test name
Test status
Simulation time 13510429 ps
CPU time 0.58 seconds
Started Aug 09 07:15:51 PM PDT 24
Finished Aug 09 07:15:52 PM PDT 24
Peak memory 195092 kb
Host smart-960c8a60-40ec-43c1-bb78-564c0fe3f651
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350942512 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.1350942512
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.3718032028
Short name T538
Test name
Test status
Simulation time 21253056 ps
CPU time 0.57 seconds
Started Aug 09 07:15:59 PM PDT 24
Finished Aug 09 07:16:00 PM PDT 24
Peak memory 194928 kb
Host smart-68293e66-3e4b-4f82-9977-9ce61f7e834f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718032028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.3718032028
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.624537619
Short name T533
Test name
Test status
Simulation time 18025380 ps
CPU time 0.65 seconds
Started Aug 09 07:16:00 PM PDT 24
Finished Aug 09 07:16:01 PM PDT 24
Peak memory 195168 kb
Host smart-2fe7d3af-8293-48e7-ba2e-c3961a88a854
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624537619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.624537619
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.1068255062
Short name T602
Test name
Test status
Simulation time 165334294 ps
CPU time 0.62 seconds
Started Aug 09 07:16:00 PM PDT 24
Finished Aug 09 07:16:01 PM PDT 24
Peak memory 195052 kb
Host smart-87585932-bae3-48e2-b7e4-bb9b2bf09fae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068255062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.1068255062
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.3075166631
Short name T550
Test name
Test status
Simulation time 35995342 ps
CPU time 0.61 seconds
Started Aug 09 07:16:00 PM PDT 24
Finished Aug 09 07:16:01 PM PDT 24
Peak memory 195012 kb
Host smart-4c06cc34-9818-45b4-a12f-b305553ae4d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075166631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.3075166631
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.2434535446
Short name T566
Test name
Test status
Simulation time 45370161 ps
CPU time 0.59 seconds
Started Aug 09 07:16:03 PM PDT 24
Finished Aug 09 07:16:04 PM PDT 24
Peak memory 194944 kb
Host smart-37f98dd6-a727-4170-b046-20fa3a98dc9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434535446 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.2434535446
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.2431686005
Short name T570
Test name
Test status
Simulation time 160536401 ps
CPU time 0.56 seconds
Started Aug 09 07:15:59 PM PDT 24
Finished Aug 09 07:16:00 PM PDT 24
Peak memory 194940 kb
Host smart-8c2fecc8-9264-4be7-9049-0b792ce13ddc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431686005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.2431686005
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.1509533998
Short name T606
Test name
Test status
Simulation time 47893858 ps
CPU time 0.6 seconds
Started Aug 09 07:16:03 PM PDT 24
Finished Aug 09 07:16:04 PM PDT 24
Peak memory 195004 kb
Host smart-b7b2cee5-d485-45f0-a9c5-ee71806203cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509533998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.1509533998
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.2413301495
Short name T652
Test name
Test status
Simulation time 16431279 ps
CPU time 0.62 seconds
Started Aug 09 07:16:00 PM PDT 24
Finished Aug 09 07:16:01 PM PDT 24
Peak memory 195124 kb
Host smart-045cf785-dd86-4178-bc62-511f5e5129d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413301495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.2413301495
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.2891818498
Short name T102
Test name
Test status
Simulation time 554156949 ps
CPU time 8.58 seconds
Started Aug 09 07:15:53 PM PDT 24
Finished Aug 09 07:16:01 PM PDT 24
Peak memory 200164 kb
Host smart-cd256bd9-97ad-490f-9d43-168f01b4a1b3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891818498 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.2891818498
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.3498130661
Short name T103
Test name
Test status
Simulation time 1644837438 ps
CPU time 16.23 seconds
Started Aug 09 07:16:01 PM PDT 24
Finished Aug 09 07:16:17 PM PDT 24
Peak memory 199332 kb
Host smart-6b427fd6-aa96-460a-969d-a698dc95ba1a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498130661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.3498130661
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.2351148607
Short name T624
Test name
Test status
Simulation time 105929680 ps
CPU time 0.97 seconds
Started Aug 09 07:16:01 PM PDT 24
Finished Aug 09 07:16:02 PM PDT 24
Peak memory 199676 kb
Host smart-81543e8c-b959-4e24-b556-ceeb47e3ea78
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351148607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.2351148607
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.1169226165
Short name T547
Test name
Test status
Simulation time 242549716 ps
CPU time 2.15 seconds
Started Aug 09 07:15:48 PM PDT 24
Finished Aug 09 07:15:51 PM PDT 24
Peak memory 200532 kb
Host smart-c94fec99-21f5-40e8-8606-352e507692a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169226165 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.1169226165
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.3289590561
Short name T120
Test name
Test status
Simulation time 64739415 ps
CPU time 0.9 seconds
Started Aug 09 07:15:44 PM PDT 24
Finished Aug 09 07:15:45 PM PDT 24
Peak memory 199668 kb
Host smart-78683907-d48e-451f-bf31-59389762f44d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289590561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.3289590561
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.1657728597
Short name T600
Test name
Test status
Simulation time 14435002 ps
CPU time 0.57 seconds
Started Aug 09 07:15:46 PM PDT 24
Finished Aug 09 07:15:47 PM PDT 24
Peak memory 194988 kb
Host smart-da12c157-a550-42b6-b444-e8c14dd87322
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657728597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.1657728597
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.2445077096
Short name T114
Test name
Test status
Simulation time 68958492 ps
CPU time 1.64 seconds
Started Aug 09 07:15:50 PM PDT 24
Finished Aug 09 07:15:52 PM PDT 24
Peak memory 200136 kb
Host smart-7dd4d181-ed5e-4621-8bb6-9f75a54adfbb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445077096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.2445077096
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.2371461381
Short name T595
Test name
Test status
Simulation time 39174917 ps
CPU time 2.17 seconds
Started Aug 09 07:15:45 PM PDT 24
Finished Aug 09 07:15:48 PM PDT 24
Peak memory 200148 kb
Host smart-09daaa6b-c85b-4f3e-a848-506b7fc1f28b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371461381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.2371461381
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.1287683240
Short name T126
Test name
Test status
Simulation time 92072710 ps
CPU time 2.82 seconds
Started Aug 09 07:15:46 PM PDT 24
Finished Aug 09 07:15:49 PM PDT 24
Peak memory 200160 kb
Host smart-c727a3c8-e884-4a08-a673-2099ad1dd0c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287683240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.1287683240
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.631877457
Short name T555
Test name
Test status
Simulation time 10857973 ps
CPU time 0.58 seconds
Started Aug 09 07:16:07 PM PDT 24
Finished Aug 09 07:16:08 PM PDT 24
Peak memory 194964 kb
Host smart-93d22b65-289f-4e2c-bc49-eaf4c713a246
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631877457 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.631877457
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.3650021388
Short name T571
Test name
Test status
Simulation time 75558303 ps
CPU time 0.61 seconds
Started Aug 09 07:15:54 PM PDT 24
Finished Aug 09 07:15:55 PM PDT 24
Peak memory 195052 kb
Host smart-ae56447a-98ab-4749-bb5f-1180f8ce4953
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650021388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.3650021388
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.1248807320
Short name T563
Test name
Test status
Simulation time 24024056 ps
CPU time 0.57 seconds
Started Aug 09 07:16:04 PM PDT 24
Finished Aug 09 07:16:05 PM PDT 24
Peak memory 194984 kb
Host smart-7293dc79-6545-4bec-be91-d03ca7e59c52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248807320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.1248807320
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.3942646877
Short name T542
Test name
Test status
Simulation time 56370852 ps
CPU time 0.63 seconds
Started Aug 09 07:15:52 PM PDT 24
Finished Aug 09 07:15:53 PM PDT 24
Peak memory 195128 kb
Host smart-49545a0e-387c-4d3d-a3c6-4866a4856bec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942646877 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.3942646877
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.4287452545
Short name T567
Test name
Test status
Simulation time 51633526 ps
CPU time 0.58 seconds
Started Aug 09 07:15:57 PM PDT 24
Finished Aug 09 07:15:58 PM PDT 24
Peak memory 195040 kb
Host smart-38783fc3-7d02-436d-ae3c-40292f48a69c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287452545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.4287452545
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.33073915
Short name T626
Test name
Test status
Simulation time 34056472 ps
CPU time 0.63 seconds
Started Aug 09 07:16:02 PM PDT 24
Finished Aug 09 07:16:03 PM PDT 24
Peak memory 195164 kb
Host smart-a1520e43-74a9-408b-ab49-8713ee0a6bea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33073915 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.33073915
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.3511907978
Short name T564
Test name
Test status
Simulation time 42383828 ps
CPU time 0.58 seconds
Started Aug 09 07:16:04 PM PDT 24
Finished Aug 09 07:16:04 PM PDT 24
Peak memory 195036 kb
Host smart-b310aa5c-c167-4ded-ad78-2cb6bdc182a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511907978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.3511907978
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.603941165
Short name T534
Test name
Test status
Simulation time 12727194 ps
CPU time 0.6 seconds
Started Aug 09 07:15:52 PM PDT 24
Finished Aug 09 07:15:53 PM PDT 24
Peak memory 195160 kb
Host smart-181f1de0-6cfe-436a-a1e6-4e669a6221f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603941165 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.603941165
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.3584472733
Short name T596
Test name
Test status
Simulation time 22878804 ps
CPU time 0.62 seconds
Started Aug 09 07:16:01 PM PDT 24
Finished Aug 09 07:16:01 PM PDT 24
Peak memory 194984 kb
Host smart-30ac874b-77ba-426a-aa7a-ae5282776f96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584472733 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.3584472733
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.977598865
Short name T628
Test name
Test status
Simulation time 75455650 ps
CPU time 0.6 seconds
Started Aug 09 07:15:59 PM PDT 24
Finished Aug 09 07:16:00 PM PDT 24
Peak memory 195024 kb
Host smart-fcc4cb69-4db2-4a8a-9c52-b7709a4e279e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977598865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.977598865
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.3883824813
Short name T104
Test name
Test status
Simulation time 599010654 ps
CPU time 8.09 seconds
Started Aug 09 07:16:01 PM PDT 24
Finished Aug 09 07:16:09 PM PDT 24
Peak memory 200176 kb
Host smart-1ab8cbbf-3acd-4937-a3a7-983f0417ed00
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883824813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.3883824813
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.3943584395
Short name T541
Test name
Test status
Simulation time 4206377824 ps
CPU time 15.9 seconds
Started Aug 09 07:15:45 PM PDT 24
Finished Aug 09 07:16:01 PM PDT 24
Peak memory 200152 kb
Host smart-942da1d2-152b-4072-90c2-30bce01dc888
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943584395 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.3943584395
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.1018314090
Short name T627
Test name
Test status
Simulation time 39141411 ps
CPU time 0.97 seconds
Started Aug 09 07:15:50 PM PDT 24
Finished Aug 09 07:15:52 PM PDT 24
Peak memory 199984 kb
Host smart-f53df132-5743-4b14-a80d-1beea2d2e2d4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018314090 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.1018314090
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.3322328023
Short name T572
Test name
Test status
Simulation time 447413821881 ps
CPU time 895.69 seconds
Started Aug 09 07:16:02 PM PDT 24
Finished Aug 09 07:30:58 PM PDT 24
Peak memory 216604 kb
Host smart-1ada2090-256d-463f-af8a-4592d0e1f4a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322328023 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.3322328023
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.797796644
Short name T601
Test name
Test status
Simulation time 30477385 ps
CPU time 0.61 seconds
Started Aug 09 07:15:52 PM PDT 24
Finished Aug 09 07:15:52 PM PDT 24
Peak memory 195288 kb
Host smart-bc3c2258-e87a-4b2c-a9ec-c09d52e91b7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797796644 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.797796644
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.1533832450
Short name T117
Test name
Test status
Simulation time 33835901 ps
CPU time 1.67 seconds
Started Aug 09 07:15:58 PM PDT 24
Finished Aug 09 07:16:00 PM PDT 24
Peak memory 200124 kb
Host smart-81b94535-d589-4ee1-94f5-68d74b2e5beb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533832450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.1533832450
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.1256163769
Short name T546
Test name
Test status
Simulation time 353688782 ps
CPU time 3.69 seconds
Started Aug 09 07:15:58 PM PDT 24
Finished Aug 09 07:16:02 PM PDT 24
Peak memory 200148 kb
Host smart-51a2e865-24b9-4072-85a8-e423eca60fe1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256163769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.1256163769
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.806193205
Short name T129
Test name
Test status
Simulation time 180687527 ps
CPU time 1.68 seconds
Started Aug 09 07:15:51 PM PDT 24
Finished Aug 09 07:15:53 PM PDT 24
Peak memory 200168 kb
Host smart-8f2dd20d-5267-46ae-b82e-a95c358ffe02
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806193205 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.806193205
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.1337976544
Short name T637
Test name
Test status
Simulation time 111166829 ps
CPU time 0.61 seconds
Started Aug 09 07:15:54 PM PDT 24
Finished Aug 09 07:15:55 PM PDT 24
Peak memory 194988 kb
Host smart-0f35defd-d121-4d6b-9877-cc900abd068d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337976544 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.1337976544
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.2202874193
Short name T610
Test name
Test status
Simulation time 43757828 ps
CPU time 0.6 seconds
Started Aug 09 07:16:04 PM PDT 24
Finished Aug 09 07:16:04 PM PDT 24
Peak memory 195080 kb
Host smart-9a1f791e-2399-49c1-bdae-5023c6827888
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202874193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.2202874193
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.3647713218
Short name T659
Test name
Test status
Simulation time 23217321 ps
CPU time 0.61 seconds
Started Aug 09 07:16:05 PM PDT 24
Finished Aug 09 07:16:06 PM PDT 24
Peak memory 194996 kb
Host smart-4e7f0847-435d-4d41-a7b7-c3df7330e8be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647713218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.3647713218
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.3707131329
Short name T576
Test name
Test status
Simulation time 50477384 ps
CPU time 0.59 seconds
Started Aug 09 07:15:56 PM PDT 24
Finished Aug 09 07:15:57 PM PDT 24
Peak memory 194988 kb
Host smart-aeb005d7-cadf-471b-b4a6-2811f9c5862c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707131329 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.3707131329
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.2439443176
Short name T623
Test name
Test status
Simulation time 48311734 ps
CPU time 0.57 seconds
Started Aug 09 07:15:59 PM PDT 24
Finished Aug 09 07:16:00 PM PDT 24
Peak memory 195080 kb
Host smart-96f40ba8-7598-4cb5-a3aa-519ad86117b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439443176 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.2439443176
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.3262737114
Short name T554
Test name
Test status
Simulation time 13222785 ps
CPU time 0.58 seconds
Started Aug 09 07:16:04 PM PDT 24
Finished Aug 09 07:16:05 PM PDT 24
Peak memory 194944 kb
Host smart-5ac0b50f-5034-429d-b77f-a835df3000a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262737114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.3262737114
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.949695238
Short name T638
Test name
Test status
Simulation time 30434077 ps
CPU time 0.63 seconds
Started Aug 09 07:16:04 PM PDT 24
Finished Aug 09 07:16:04 PM PDT 24
Peak memory 195072 kb
Host smart-12679825-811a-426d-994c-7026ec338483
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949695238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.949695238
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.1808553309
Short name T577
Test name
Test status
Simulation time 15418788 ps
CPU time 0.58 seconds
Started Aug 09 07:15:59 PM PDT 24
Finished Aug 09 07:16:00 PM PDT 24
Peak memory 195020 kb
Host smart-9dfdd638-7f91-41a5-97e5-d26a3310ac82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808553309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.1808553309
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.3880255844
Short name T549
Test name
Test status
Simulation time 23206769 ps
CPU time 0.6 seconds
Started Aug 09 07:16:04 PM PDT 24
Finished Aug 09 07:16:05 PM PDT 24
Peak memory 195052 kb
Host smart-dd0554ef-9369-45d5-b026-99b908e064a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880255844 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.3880255844
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.4123766687
Short name T641
Test name
Test status
Simulation time 52741390 ps
CPU time 0.62 seconds
Started Aug 09 07:15:59 PM PDT 24
Finished Aug 09 07:16:00 PM PDT 24
Peak memory 195156 kb
Host smart-58acab36-754f-47dc-8902-5bb4e77f9e34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123766687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.4123766687
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.3342739522
Short name T560
Test name
Test status
Simulation time 18008253180 ps
CPU time 78.19 seconds
Started Aug 09 07:15:50 PM PDT 24
Finished Aug 09 07:17:08 PM PDT 24
Peak memory 215852 kb
Host smart-5bb9f7cd-430d-4561-830b-89638cf0647d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342739522 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.3342739522
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.2346902457
Short name T644
Test name
Test status
Simulation time 104769551 ps
CPU time 0.94 seconds
Started Aug 09 07:15:44 PM PDT 24
Finished Aug 09 07:15:45 PM PDT 24
Peak memory 199696 kb
Host smart-eaeb7aa7-336e-45c7-92be-3a373304aa84
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346902457 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.2346902457
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.2544819388
Short name T565
Test name
Test status
Simulation time 20773551 ps
CPU time 0.6 seconds
Started Aug 09 07:15:47 PM PDT 24
Finished Aug 09 07:15:47 PM PDT 24
Peak memory 195144 kb
Host smart-a1116ec7-27e6-4ecf-989a-8dfb04c75f1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544819388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.2544819388
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.959115834
Short name T650
Test name
Test status
Simulation time 238451461 ps
CPU time 1.66 seconds
Started Aug 09 07:16:00 PM PDT 24
Finished Aug 09 07:16:02 PM PDT 24
Peak memory 200096 kb
Host smart-498235d3-c614-43a0-b2ee-8de50ca2e9c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959115834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr_
outstanding.959115834
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.1049948537
Short name T642
Test name
Test status
Simulation time 857727851 ps
CPU time 2.24 seconds
Started Aug 09 07:15:51 PM PDT 24
Finished Aug 09 07:15:53 PM PDT 24
Peak memory 200096 kb
Host smart-2844aa69-8c98-4f6f-80b0-43f0aca8eef4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049948537 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.1049948537
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.3483346070
Short name T645
Test name
Test status
Simulation time 156486885 ps
CPU time 2.8 seconds
Started Aug 09 07:15:51 PM PDT 24
Finished Aug 09 07:15:54 PM PDT 24
Peak memory 200080 kb
Host smart-433f9174-e7c5-43d3-aa89-7e2b61228507
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483346070 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.3483346070
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.2806674195
Short name T556
Test name
Test status
Simulation time 32438265 ps
CPU time 1.73 seconds
Started Aug 09 07:15:41 PM PDT 24
Finished Aug 09 07:15:42 PM PDT 24
Peak memory 200204 kb
Host smart-ed7460ef-1f0c-475a-b593-c00884a800d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806674195 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.2806674195
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.1053849398
Short name T634
Test name
Test status
Simulation time 27852798 ps
CPU time 0.83 seconds
Started Aug 09 07:15:44 PM PDT 24
Finished Aug 09 07:15:45 PM PDT 24
Peak memory 199372 kb
Host smart-3fa896c1-789e-4807-950f-56ec253e54c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053849398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.1053849398
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.3703923205
Short name T614
Test name
Test status
Simulation time 26888730 ps
CPU time 0.57 seconds
Started Aug 09 07:15:43 PM PDT 24
Finished Aug 09 07:15:43 PM PDT 24
Peak memory 195060 kb
Host smart-4db2046d-2da1-44b5-8fd3-c5c8a02137a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703923205 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.3703923205
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.2786717955
Short name T607
Test name
Test status
Simulation time 103087956 ps
CPU time 1.65 seconds
Started Aug 09 07:15:47 PM PDT 24
Finished Aug 09 07:15:49 PM PDT 24
Peak memory 199916 kb
Host smart-fc39ba44-dd5c-46f8-9e93-0633a3c83111
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786717955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.2786717955
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.3400150214
Short name T575
Test name
Test status
Simulation time 28707772 ps
CPU time 1.6 seconds
Started Aug 09 07:16:03 PM PDT 24
Finished Aug 09 07:16:04 PM PDT 24
Peak memory 200124 kb
Host smart-23e13465-e5a7-4fdc-ab74-684e51c530c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400150214 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.3400150214
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.3009729541
Short name T67
Test name
Test status
Simulation time 446836430 ps
CPU time 2.81 seconds
Started Aug 09 07:15:54 PM PDT 24
Finished Aug 09 07:15:57 PM PDT 24
Peak memory 200208 kb
Host smart-d779983c-43e3-45fd-888b-3973b00df08c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009729541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.3009729541
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.4049581223
Short name T585
Test name
Test status
Simulation time 209872170 ps
CPU time 2.32 seconds
Started Aug 09 07:15:59 PM PDT 24
Finished Aug 09 07:16:02 PM PDT 24
Peak memory 200164 kb
Host smart-dd72f724-9bec-4920-aff9-9fe9a7f3cb9b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049581223 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.4049581223
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3578655414
Short name T568
Test name
Test status
Simulation time 21736071 ps
CPU time 0.69 seconds
Started Aug 09 07:15:53 PM PDT 24
Finished Aug 09 07:15:54 PM PDT 24
Peak memory 197624 kb
Host smart-74c856c5-8570-4b88-a9c2-a76937a90f14
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578655414 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.3578655414
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.2627422263
Short name T653
Test name
Test status
Simulation time 13620243 ps
CPU time 0.58 seconds
Started Aug 09 07:16:01 PM PDT 24
Finished Aug 09 07:16:02 PM PDT 24
Peak memory 195016 kb
Host smart-1796c898-9c1d-4766-b539-12e7e4a362c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627422263 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.2627422263
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3692025096
Short name T643
Test name
Test status
Simulation time 77415511 ps
CPU time 1.65 seconds
Started Aug 09 07:15:42 PM PDT 24
Finished Aug 09 07:15:44 PM PDT 24
Peak memory 200084 kb
Host smart-664a3dbb-0b27-4b79-9d16-4e22dd12f815
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692025096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.3692025096
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.3146686551
Short name T592
Test name
Test status
Simulation time 69651932 ps
CPU time 1.65 seconds
Started Aug 09 07:15:43 PM PDT 24
Finished Aug 09 07:15:44 PM PDT 24
Peak memory 200108 kb
Host smart-6619e623-e06c-4294-9c29-a50a0a84ffc6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146686551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.3146686551
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.1433836882
Short name T646
Test name
Test status
Simulation time 386456958 ps
CPU time 1.87 seconds
Started Aug 09 07:15:44 PM PDT 24
Finished Aug 09 07:15:46 PM PDT 24
Peak memory 200112 kb
Host smart-d9cd0175-0dc2-4ad2-a09b-cff63cf27776
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433836882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.1433836882
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.4253712086
Short name T632
Test name
Test status
Simulation time 50603718 ps
CPU time 3.13 seconds
Started Aug 09 07:15:46 PM PDT 24
Finished Aug 09 07:15:49 PM PDT 24
Peak memory 200280 kb
Host smart-7dec570f-8d72-47e8-81bc-8aadd91d6760
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253712086 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.4253712086
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.1850699532
Short name T621
Test name
Test status
Simulation time 13513681 ps
CPU time 0.7 seconds
Started Aug 09 07:15:55 PM PDT 24
Finished Aug 09 07:15:56 PM PDT 24
Peak memory 197956 kb
Host smart-8e309a56-a5f4-4788-a040-3792bc7099f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850699532 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.1850699532
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.3858825001
Short name T562
Test name
Test status
Simulation time 21874637 ps
CPU time 0.56 seconds
Started Aug 09 07:15:47 PM PDT 24
Finished Aug 09 07:15:48 PM PDT 24
Peak memory 195020 kb
Host smart-5c84017a-1b18-42ab-8bb0-4ded0a0b2c53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858825001 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.3858825001
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.611154242
Short name T118
Test name
Test status
Simulation time 47171171 ps
CPU time 2.19 seconds
Started Aug 09 07:15:46 PM PDT 24
Finished Aug 09 07:15:48 PM PDT 24
Peak memory 200116 kb
Host smart-c8b5bc04-719e-46ba-a442-6d3c0f0f544e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611154242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr_
outstanding.611154242
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.3882880254
Short name T598
Test name
Test status
Simulation time 191814309 ps
CPU time 4.07 seconds
Started Aug 09 07:15:44 PM PDT 24
Finished Aug 09 07:15:48 PM PDT 24
Peak memory 200108 kb
Host smart-4282dbb9-66b2-43aa-9de6-e424b07b8c91
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882880254 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.3882880254
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.3178819215
Short name T593
Test name
Test status
Simulation time 320389405 ps
CPU time 2.92 seconds
Started Aug 09 07:15:43 PM PDT 24
Finished Aug 09 07:15:46 PM PDT 24
Peak memory 200164 kb
Host smart-ca573604-a5b1-4ee4-b09c-9e7de05d9844
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178819215 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.3178819215
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.1274301568
Short name T531
Test name
Test status
Simulation time 26997259536 ps
CPU time 94.74 seconds
Started Aug 09 07:15:46 PM PDT 24
Finished Aug 09 07:17:21 PM PDT 24
Peak memory 216352 kb
Host smart-a3f99dfd-608a-4741-a6db-45b64d175d19
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274301568 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.1274301568
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.3620497703
Short name T111
Test name
Test status
Simulation time 31628683 ps
CPU time 0.81 seconds
Started Aug 09 07:15:48 PM PDT 24
Finished Aug 09 07:15:49 PM PDT 24
Peak memory 199504 kb
Host smart-16c0841f-206a-40ec-8fc9-640859e2059f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620497703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.3620497703
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.147750102
Short name T611
Test name
Test status
Simulation time 42941433 ps
CPU time 0.61 seconds
Started Aug 09 07:15:44 PM PDT 24
Finished Aug 09 07:15:44 PM PDT 24
Peak memory 195028 kb
Host smart-d4a87b74-5990-4c6e-8ae1-6a53e05239ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147750102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.147750102
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.276396988
Short name T569
Test name
Test status
Simulation time 85442415 ps
CPU time 1.21 seconds
Started Aug 09 07:15:51 PM PDT 24
Finished Aug 09 07:15:52 PM PDT 24
Peak memory 200080 kb
Host smart-f0c6761f-9c2e-482d-9997-196f8811e5a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276396988 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr_
outstanding.276396988
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.3820025658
Short name T594
Test name
Test status
Simulation time 96752212 ps
CPU time 2.14 seconds
Started Aug 09 07:15:59 PM PDT 24
Finished Aug 09 07:16:02 PM PDT 24
Peak memory 200080 kb
Host smart-e1854041-599f-4cf4-9bd1-036a442b914b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820025658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.3820025658
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.2656277380
Short name T655
Test name
Test status
Simulation time 343123089 ps
CPU time 1.93 seconds
Started Aug 09 07:15:44 PM PDT 24
Finished Aug 09 07:15:46 PM PDT 24
Peak memory 200188 kb
Host smart-d4ef60c8-da62-481b-a19b-f764eb570df4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656277380 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.2656277380
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.3436965173
Short name T44
Test name
Test status
Simulation time 1403895106 ps
CPU time 38.36 seconds
Started Aug 09 07:15:58 PM PDT 24
Finished Aug 09 07:16:36 PM PDT 24
Peak memory 199852 kb
Host smart-11ecbba7-d0a2-439d-a3ee-101ff82e8c6e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3436965173 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.3436965173
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.3663320021
Short name T338
Test name
Test status
Simulation time 1316700665 ps
CPU time 64.91 seconds
Started Aug 09 07:16:00 PM PDT 24
Finished Aug 09 07:17:05 PM PDT 24
Peak memory 199804 kb
Host smart-52d8f533-2157-4b30-8b5b-09ca488446e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663320021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.3663320021
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.3247449718
Short name T47
Test name
Test status
Simulation time 13917773433 ps
CPU time 423.44 seconds
Started Aug 09 07:15:52 PM PDT 24
Finished Aug 09 07:22:56 PM PDT 24
Peak memory 713404 kb
Host smart-50496ba0-e6a0-430d-95c3-7c10019bd905
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3247449718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.3247449718
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.251888020
Short name T474
Test name
Test status
Simulation time 4829368836 ps
CPU time 69.75 seconds
Started Aug 09 07:15:54 PM PDT 24
Finished Aug 09 07:17:04 PM PDT 24
Peak memory 199928 kb
Host smart-ac6882a6-020a-4e20-ae7e-4b953e8d44aa
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251888020 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.251888020
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.3814839669
Short name T75
Test name
Test status
Simulation time 4482108256 ps
CPU time 79.14 seconds
Started Aug 09 07:16:00 PM PDT 24
Finished Aug 09 07:17:19 PM PDT 24
Peak memory 199912 kb
Host smart-8b656a44-458d-4388-b488-35c062a11f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814839669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.3814839669
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.3133470050
Short name T57
Test name
Test status
Simulation time 238900045 ps
CPU time 0.84 seconds
Started Aug 09 07:16:05 PM PDT 24
Finished Aug 09 07:16:06 PM PDT 24
Peak memory 218508 kb
Host smart-261db762-c108-4579-8b37-0aef8eab3a2b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133470050 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.3133470050
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/0.hmac_smoke.494343723
Short name T93
Test name
Test status
Simulation time 4192905250 ps
CPU time 12.62 seconds
Started Aug 09 07:15:59 PM PDT 24
Finished Aug 09 07:16:12 PM PDT 24
Peak memory 199920 kb
Host smart-c596798b-9c13-4832-87b2-06f5b256bafe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494343723 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.494343723
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.3176364147
Short name T298
Test name
Test status
Simulation time 107361443453 ps
CPU time 1413.46 seconds
Started Aug 09 07:16:08 PM PDT 24
Finished Aug 09 07:39:42 PM PDT 24
Peak memory 705268 kb
Host smart-599e760e-81dc-4a0f-9736-a985804afa30
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176364147 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.3176364147
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_stress_all_with_rand_reset.2279006031
Short name T12
Test name
Test status
Simulation time 218427687009 ps
CPU time 1526.9 seconds
Started Aug 09 07:16:17 PM PDT 24
Finished Aug 09 07:41:44 PM PDT 24
Peak memory 690528 kb
Host smart-12c5f18f-009c-4f2a-a25c-da83323abab9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2279006031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all_with_rand_reset.2279006031
Directory /workspace/0.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.hmac_test_hmac256_vectors.2433671165
Short name T449
Test name
Test status
Simulation time 3449984689 ps
CPU time 69.86 seconds
Started Aug 09 07:16:00 PM PDT 24
Finished Aug 09 07:17:10 PM PDT 24
Peak memory 199876 kb
Host smart-cb2120b6-11b0-495d-b2fd-7e9a4ae89fa4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2433671165 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac256_vectors.2433671165
Directory /workspace/0.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac384_vectors.3180901342
Short name T426
Test name
Test status
Simulation time 8002627545 ps
CPU time 53.68 seconds
Started Aug 09 07:16:03 PM PDT 24
Finished Aug 09 07:16:57 PM PDT 24
Peak memory 199876 kb
Host smart-58bbcc8f-8afe-42d9-93fc-3ed1bceac3a4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3180901342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac384_vectors.3180901342
Directory /workspace/0.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac512_vectors.780031665
Short name T258
Test name
Test status
Simulation time 9386149132 ps
CPU time 77.7 seconds
Started Aug 09 07:16:01 PM PDT 24
Finished Aug 09 07:17:19 PM PDT 24
Peak memory 199824 kb
Host smart-dd597310-3fec-478a-acff-a983c20d64e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=780031665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac512_vectors.780031665
Directory /workspace/0.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha256_vectors.3889990555
Short name T299
Test name
Test status
Simulation time 189171261886 ps
CPU time 683.63 seconds
Started Aug 09 07:15:58 PM PDT 24
Finished Aug 09 07:27:22 PM PDT 24
Peak memory 199888 kb
Host smart-40616d05-ca36-4af0-b777-5f0dd8d997f1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3889990555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha256_vectors.3889990555
Directory /workspace/0.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha384_vectors.2861397866
Short name T286
Test name
Test status
Simulation time 433753348736 ps
CPU time 2720.27 seconds
Started Aug 09 07:16:03 PM PDT 24
Finished Aug 09 08:01:24 PM PDT 24
Peak memory 216128 kb
Host smart-ab423eeb-57da-4a16-a207-0e673c31709d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2861397866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha384_vectors.2861397866
Directory /workspace/0.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha512_vectors.1562544285
Short name T335
Test name
Test status
Simulation time 277682524878 ps
CPU time 2735.06 seconds
Started Aug 09 07:16:00 PM PDT 24
Finished Aug 09 08:01:36 PM PDT 24
Peak memory 216280 kb
Host smart-b79e9081-3cb8-40b3-a467-6afe77784f36
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1562544285 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha512_vectors.1562544285
Directory /workspace/0.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.4227854030
Short name T484
Test name
Test status
Simulation time 11507982926 ps
CPU time 47.6 seconds
Started Aug 09 07:16:00 PM PDT 24
Finished Aug 09 07:16:48 PM PDT 24
Peak memory 199884 kb
Host smart-6eab633e-7779-44df-baa6-e48d1a26f04b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227854030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.4227854030
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.1533761535
Short name T170
Test name
Test status
Simulation time 12463251 ps
CPU time 0.59 seconds
Started Aug 09 07:16:05 PM PDT 24
Finished Aug 09 07:16:05 PM PDT 24
Peak memory 195928 kb
Host smart-1398edd6-e78f-402d-841d-69df54ed17a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533761535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.1533761535
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.2054471410
Short name T488
Test name
Test status
Simulation time 393407369 ps
CPU time 22.86 seconds
Started Aug 09 07:16:02 PM PDT 24
Finished Aug 09 07:16:25 PM PDT 24
Peak memory 199856 kb
Host smart-b3310414-151e-4b12-9772-100199e09fda
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2054471410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.2054471410
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.1466274121
Short name T328
Test name
Test status
Simulation time 2421157568 ps
CPU time 32.17 seconds
Started Aug 09 07:16:17 PM PDT 24
Finished Aug 09 07:16:50 PM PDT 24
Peak memory 199936 kb
Host smart-27c1a905-8057-42e1-ab9d-4767c7d2fa8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466274121 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.1466274121
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.2459814711
Short name T413
Test name
Test status
Simulation time 6449207937 ps
CPU time 1148.11 seconds
Started Aug 09 07:16:06 PM PDT 24
Finished Aug 09 07:35:14 PM PDT 24
Peak memory 776624 kb
Host smart-1b689c6f-7559-4ee8-95da-62010618155e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2459814711 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.2459814711
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.2822207022
Short name T269
Test name
Test status
Simulation time 61369107761 ps
CPU time 206.77 seconds
Started Aug 09 07:16:03 PM PDT 24
Finished Aug 09 07:19:30 PM PDT 24
Peak memory 199908 kb
Host smart-fa899d04-824e-49df-bbb4-5d42095c74cd
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822207022 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.2822207022
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.1141400088
Short name T329
Test name
Test status
Simulation time 25548874341 ps
CPU time 103.55 seconds
Started Aug 09 07:16:02 PM PDT 24
Finished Aug 09 07:17:45 PM PDT 24
Peak memory 199968 kb
Host smart-8f61e2cd-90b6-4d14-af38-8d4cca1129a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141400088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.1141400088
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.2056835254
Short name T55
Test name
Test status
Simulation time 36212864 ps
CPU time 0.81 seconds
Started Aug 09 07:16:01 PM PDT 24
Finished Aug 09 07:16:02 PM PDT 24
Peak memory 218480 kb
Host smart-7a9a6142-a152-4f36-bc75-6d8f6b5d844b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056835254 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.2056835254
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.2465729877
Short name T300
Test name
Test status
Simulation time 325126289 ps
CPU time 15.13 seconds
Started Aug 09 07:16:17 PM PDT 24
Finished Aug 09 07:16:32 PM PDT 24
Peak memory 199908 kb
Host smart-ec8c56c8-146c-47e5-b48a-8012353a7f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465729877 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.2465729877
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.308743509
Short name T387
Test name
Test status
Simulation time 3785373200 ps
CPU time 706.81 seconds
Started Aug 09 07:16:06 PM PDT 24
Finished Aug 09 07:27:53 PM PDT 24
Peak memory 654220 kb
Host smart-220966b5-c310-4ec6-ad3e-4f3771d83eb0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308743509 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.308743509
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_stress_all_with_rand_reset.1862880070
Short name T35
Test name
Test status
Simulation time 18949572039 ps
CPU time 2230.26 seconds
Started Aug 09 07:16:04 PM PDT 24
Finished Aug 09 07:53:15 PM PDT 24
Peak memory 789576 kb
Host smart-2b86b39d-ec05-438d-870f-082d8f225640
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1862880070 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all_with_rand_reset.1862880070
Directory /workspace/1.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.hmac_test_hmac256_vectors.2208883278
Short name T377
Test name
Test status
Simulation time 5347742269 ps
CPU time 43.5 seconds
Started Aug 09 07:16:16 PM PDT 24
Finished Aug 09 07:17:00 PM PDT 24
Peak memory 199900 kb
Host smart-d2fbedfa-b7d4-42b0-a313-8cd47afef653
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2208883278 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac256_vectors.2208883278
Directory /workspace/1.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac384_vectors.984993970
Short name T214
Test name
Test status
Simulation time 2231368329 ps
CPU time 91.3 seconds
Started Aug 09 07:16:05 PM PDT 24
Finished Aug 09 07:17:37 PM PDT 24
Peak memory 199896 kb
Host smart-e401786b-d9bf-4775-b69b-83234e00359d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=984993970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac384_vectors.984993970
Directory /workspace/1.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac512_vectors.891140385
Short name T192
Test name
Test status
Simulation time 22623412871 ps
CPU time 77.6 seconds
Started Aug 09 07:16:15 PM PDT 24
Finished Aug 09 07:17:33 PM PDT 24
Peak memory 199900 kb
Host smart-5ec7979a-0aec-47f6-8edb-a7eae3f752eb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=891140385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac512_vectors.891140385
Directory /workspace/1.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha256_vectors.642653229
Short name T277
Test name
Test status
Simulation time 136479380937 ps
CPU time 584.84 seconds
Started Aug 09 07:16:00 PM PDT 24
Finished Aug 09 07:25:45 PM PDT 24
Peak memory 200052 kb
Host smart-9274f36e-31c4-4e59-8fbf-53f8c41e7e94
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=642653229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha256_vectors.642653229
Directory /workspace/1.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha384_vectors.3537025160
Short name T166
Test name
Test status
Simulation time 217685426886 ps
CPU time 2382.59 seconds
Started Aug 09 07:16:11 PM PDT 24
Finished Aug 09 07:55:54 PM PDT 24
Peak memory 215824 kb
Host smart-b7bd2f98-2a80-422a-9a50-310a67c7b101
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3537025160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha384_vectors.3537025160
Directory /workspace/1.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha512_vectors.3556630985
Short name T432
Test name
Test status
Simulation time 352866847454 ps
CPU time 2341.35 seconds
Started Aug 09 07:16:12 PM PDT 24
Finished Aug 09 07:55:14 PM PDT 24
Peak memory 216228 kb
Host smart-b9c0aa3e-2093-4af4-adbd-195cc2b0c972
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3556630985 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha512_vectors.3556630985
Directory /workspace/1.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.2049069418
Short name T149
Test name
Test status
Simulation time 1730646378 ps
CPU time 8.68 seconds
Started Aug 09 07:15:58 PM PDT 24
Finished Aug 09 07:16:07 PM PDT 24
Peak memory 199736 kb
Host smart-4ab2b276-ecdf-44cc-a03f-c9ffb46bf488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049069418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.2049069418
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.1189633897
Short name T288
Test name
Test status
Simulation time 15994330 ps
CPU time 0.58 seconds
Started Aug 09 07:16:23 PM PDT 24
Finished Aug 09 07:16:24 PM PDT 24
Peak memory 195688 kb
Host smart-7cc8a740-9488-4310-8c08-a7a793fac3ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189633897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.1189633897
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.486116846
Short name T429
Test name
Test status
Simulation time 944950226 ps
CPU time 54.79 seconds
Started Aug 09 07:16:26 PM PDT 24
Finished Aug 09 07:17:21 PM PDT 24
Peak memory 199852 kb
Host smart-4a37c1b1-aca8-4b18-9b7a-290f4bbb3194
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=486116846 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.486116846
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.3064942834
Short name T440
Test name
Test status
Simulation time 7134508103 ps
CPU time 46.9 seconds
Started Aug 09 07:16:26 PM PDT 24
Finished Aug 09 07:17:13 PM PDT 24
Peak memory 199872 kb
Host smart-154498b9-bea3-4ae5-b83d-bcaae1b90be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064942834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.3064942834
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.2619990210
Short name T195
Test name
Test status
Simulation time 2368188046 ps
CPU time 217.34 seconds
Started Aug 09 07:16:24 PM PDT 24
Finished Aug 09 07:20:01 PM PDT 24
Peak memory 591840 kb
Host smart-ac7c8af8-7978-4d83-9917-36c8285d1ba1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2619990210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.2619990210
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.1096283551
Short name T380
Test name
Test status
Simulation time 3508097942 ps
CPU time 181.6 seconds
Started Aug 09 07:16:26 PM PDT 24
Finished Aug 09 07:19:28 PM PDT 24
Peak memory 199784 kb
Host smart-c213edb2-4337-42ef-adf5-bd3e6e18d0de
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096283551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.1096283551
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.1834801822
Short name T183
Test name
Test status
Simulation time 6209157920 ps
CPU time 82.71 seconds
Started Aug 09 07:16:17 PM PDT 24
Finished Aug 09 07:17:40 PM PDT 24
Peak memory 199916 kb
Host smart-9d4c1d8e-11bb-48fa-9b88-d12e1a71fdde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834801822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.1834801822
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.3300287979
Short name T385
Test name
Test status
Simulation time 58180224 ps
CPU time 2.86 seconds
Started Aug 09 07:16:19 PM PDT 24
Finished Aug 09 07:16:22 PM PDT 24
Peak memory 199796 kb
Host smart-f73ed1f2-68a9-4bdb-b810-905ab75f6bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300287979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.3300287979
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.1494477326
Short name T284
Test name
Test status
Simulation time 38311782094 ps
CPU time 350.28 seconds
Started Aug 09 07:16:24 PM PDT 24
Finished Aug 09 07:22:14 PM PDT 24
Peak memory 216280 kb
Host smart-d92a1a34-1f29-4a9d-a7fd-71e3f26cf5fa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494477326 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.1494477326
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.2392271554
Short name T95
Test name
Test status
Simulation time 884672543 ps
CPU time 46.52 seconds
Started Aug 09 07:16:30 PM PDT 24
Finished Aug 09 07:17:16 PM PDT 24
Peak memory 199844 kb
Host smart-438ef96e-14c2-4aeb-ab43-5dcc6b8c51dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392271554 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.2392271554
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.2849506556
Short name T181
Test name
Test status
Simulation time 39613847 ps
CPU time 0.57 seconds
Started Aug 09 07:16:30 PM PDT 24
Finished Aug 09 07:16:30 PM PDT 24
Peak memory 196628 kb
Host smart-ab494830-96b4-42ce-818d-345897261dbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849506556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.2849506556
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.3671163695
Short name T395
Test name
Test status
Simulation time 721086722 ps
CPU time 39.57 seconds
Started Aug 09 07:16:29 PM PDT 24
Finished Aug 09 07:17:09 PM PDT 24
Peak memory 199864 kb
Host smart-f0c68166-6fc0-406f-a174-cbc7ca8923a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3671163695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.3671163695
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.3370652314
Short name T341
Test name
Test status
Simulation time 451597906 ps
CPU time 24.02 seconds
Started Aug 09 07:16:30 PM PDT 24
Finished Aug 09 07:16:54 PM PDT 24
Peak memory 199832 kb
Host smart-7cf04415-cfd2-426b-8b4c-08cf45b3681d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370652314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.3370652314
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.4114710327
Short name T37
Test name
Test status
Simulation time 15577162161 ps
CPU time 613.73 seconds
Started Aug 09 07:16:24 PM PDT 24
Finished Aug 09 07:26:38 PM PDT 24
Peak memory 491296 kb
Host smart-75b6cebf-fe70-4a19-8ef7-d6cef2f3e761
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4114710327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.4114710327
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.3047553086
Short name T336
Test name
Test status
Simulation time 1830074718 ps
CPU time 100.49 seconds
Started Aug 09 07:16:31 PM PDT 24
Finished Aug 09 07:18:11 PM PDT 24
Peak memory 199816 kb
Host smart-911903e6-2ee6-4b10-b5b7-a2ae9a86f300
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047553086 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.3047553086
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.4045759417
Short name T207
Test name
Test status
Simulation time 2696752993 ps
CPU time 48.67 seconds
Started Aug 09 07:16:23 PM PDT 24
Finished Aug 09 07:17:12 PM PDT 24
Peak memory 199952 kb
Host smart-38d8ac99-81d0-4db6-b42c-4b81127948dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045759417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.4045759417
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.3585737826
Short name T29
Test name
Test status
Simulation time 987041175 ps
CPU time 12.62 seconds
Started Aug 09 07:16:30 PM PDT 24
Finished Aug 09 07:16:43 PM PDT 24
Peak memory 199916 kb
Host smart-7dd6546c-9853-4f5c-a530-5b8283b40dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585737826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.3585737826
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.4032924847
Short name T65
Test name
Test status
Simulation time 58156000816 ps
CPU time 2283.76 seconds
Started Aug 09 07:16:24 PM PDT 24
Finished Aug 09 07:54:29 PM PDT 24
Peak memory 760316 kb
Host smart-25e3cb1b-492c-4c77-90ae-25b99adf8b18
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032924847 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.4032924847
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.2744266752
Short name T176
Test name
Test status
Simulation time 3965778520 ps
CPU time 23.74 seconds
Started Aug 09 07:16:19 PM PDT 24
Finished Aug 09 07:16:43 PM PDT 24
Peak memory 199880 kb
Host smart-f6e6e292-c520-4da6-9714-62558ab5870c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744266752 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.2744266752
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.1148423667
Short name T482
Test name
Test status
Simulation time 11500179 ps
CPU time 0.57 seconds
Started Aug 09 07:16:27 PM PDT 24
Finished Aug 09 07:16:28 PM PDT 24
Peak memory 194884 kb
Host smart-b8021535-0746-46ff-b850-81623f23ac00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148423667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.1148423667
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.925559431
Short name T529
Test name
Test status
Simulation time 6085527931 ps
CPU time 34.81 seconds
Started Aug 09 07:16:19 PM PDT 24
Finished Aug 09 07:16:54 PM PDT 24
Peak memory 199884 kb
Host smart-e8d2b47e-2730-4e45-b9c3-20151b5e2191
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=925559431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.925559431
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.4083688998
Short name T143
Test name
Test status
Simulation time 240154950 ps
CPU time 11.96 seconds
Started Aug 09 07:16:22 PM PDT 24
Finished Aug 09 07:16:34 PM PDT 24
Peak memory 199816 kb
Host smart-2a86d7b6-dd38-479a-a35f-9ac0a1afa8e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083688998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.4083688998
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.2617744045
Short name T155
Test name
Test status
Simulation time 12297854373 ps
CPU time 535.34 seconds
Started Aug 09 07:16:26 PM PDT 24
Finished Aug 09 07:25:22 PM PDT 24
Peak memory 508940 kb
Host smart-9d902d72-624e-4e2c-8703-d65df4f6fe4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2617744045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.2617744045
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_long_msg.2606248325
Short name T319
Test name
Test status
Simulation time 7165349716 ps
CPU time 90.95 seconds
Started Aug 09 07:16:24 PM PDT 24
Finished Aug 09 07:17:56 PM PDT 24
Peak memory 199888 kb
Host smart-a26a793d-f046-45f4-866b-7bc8fcc355c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606248325 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.2606248325
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.1023836243
Short name T43
Test name
Test status
Simulation time 1630264370 ps
CPU time 11.22 seconds
Started Aug 09 07:16:26 PM PDT 24
Finished Aug 09 07:16:37 PM PDT 24
Peak memory 199816 kb
Host smart-b8f376b2-8eac-49d5-91ee-c444f253f81c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023836243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.1023836243
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.1400490487
Short name T10
Test name
Test status
Simulation time 10417104850 ps
CPU time 802.09 seconds
Started Aug 09 07:16:19 PM PDT 24
Finished Aug 09 07:29:41 PM PDT 24
Peak memory 665576 kb
Host smart-8f046474-1e51-4814-a0b8-22c5182c9b1b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400490487 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.1400490487
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.1774260986
Short name T94
Test name
Test status
Simulation time 1897914450 ps
CPU time 101.94 seconds
Started Aug 09 07:16:25 PM PDT 24
Finished Aug 09 07:18:07 PM PDT 24
Peak memory 199884 kb
Host smart-3411d160-e86c-49bf-85a3-62c6f8534214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774260986 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.1774260986
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_alert_test.760648552
Short name T51
Test name
Test status
Simulation time 27034045 ps
CPU time 0.6 seconds
Started Aug 09 07:16:25 PM PDT 24
Finished Aug 09 07:16:25 PM PDT 24
Peak memory 195924 kb
Host smart-4b639dff-1399-41e1-9c9d-4aa1d74b5e83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760648552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.760648552
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.3892567394
Short name T508
Test name
Test status
Simulation time 1488975251 ps
CPU time 47.98 seconds
Started Aug 09 07:16:23 PM PDT 24
Finished Aug 09 07:17:11 PM PDT 24
Peak memory 199832 kb
Host smart-f4e05cbe-c56a-4549-acec-195f53ebd982
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3892567394 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.3892567394
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.2649759210
Short name T514
Test name
Test status
Simulation time 5174701880 ps
CPU time 16.77 seconds
Started Aug 09 07:16:20 PM PDT 24
Finished Aug 09 07:16:37 PM PDT 24
Peak memory 199892 kb
Host smart-ed537afe-6058-46ce-82f9-f46b07b760fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649759210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.2649759210
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.1822222730
Short name T227
Test name
Test status
Simulation time 21333362283 ps
CPU time 1123.63 seconds
Started Aug 09 07:16:28 PM PDT 24
Finished Aug 09 07:35:12 PM PDT 24
Peak memory 737456 kb
Host smart-6efb73b8-bf1e-4149-a90f-854194184524
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1822222730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.1822222730
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.798098327
Short name T522
Test name
Test status
Simulation time 29131609842 ps
CPU time 87.83 seconds
Started Aug 09 07:16:33 PM PDT 24
Finished Aug 09 07:18:00 PM PDT 24
Peak memory 199936 kb
Host smart-3e1f7ebb-4d36-4c49-b8e6-ded7bd7c94b6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798098327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.798098327
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.4194049244
Short name T243
Test name
Test status
Simulation time 1480949390 ps
CPU time 80.97 seconds
Started Aug 09 07:16:26 PM PDT 24
Finished Aug 09 07:17:47 PM PDT 24
Peak memory 199824 kb
Host smart-d5e44bc8-57c0-47c0-aaf5-2bc28a089dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194049244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.4194049244
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.3134917518
Short name T33
Test name
Test status
Simulation time 312934089 ps
CPU time 14.75 seconds
Started Aug 09 07:16:26 PM PDT 24
Finished Aug 09 07:16:40 PM PDT 24
Peak memory 199860 kb
Host smart-7662a5da-2e30-403c-9a8d-e70279f81421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134917518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.3134917518
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.3932245300
Short name T230
Test name
Test status
Simulation time 409617659 ps
CPU time 8.8 seconds
Started Aug 09 07:16:29 PM PDT 24
Finished Aug 09 07:16:38 PM PDT 24
Peak memory 199840 kb
Host smart-e028ae8d-20d8-424e-8abf-caf352182f2b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932245300 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.3932245300
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.2676256732
Short name T97
Test name
Test status
Simulation time 8526749967 ps
CPU time 111.02 seconds
Started Aug 09 07:16:26 PM PDT 24
Finished Aug 09 07:18:17 PM PDT 24
Peak memory 199880 kb
Host smart-e25cf2d8-0a2a-4d5b-99e3-d8209df6d6ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676256732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.2676256732
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.3620329036
Short name T342
Test name
Test status
Simulation time 18166740 ps
CPU time 0.55 seconds
Started Aug 09 07:16:31 PM PDT 24
Finished Aug 09 07:16:32 PM PDT 24
Peak memory 194920 kb
Host smart-0252bf69-9f75-47c4-a776-0c93c4772d51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620329036 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.3620329036
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.4109407781
Short name T500
Test name
Test status
Simulation time 461378599 ps
CPU time 26.35 seconds
Started Aug 09 07:16:28 PM PDT 24
Finished Aug 09 07:16:54 PM PDT 24
Peak memory 199848 kb
Host smart-295c5370-2c62-4635-b944-8c75f95aa64b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4109407781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.4109407781
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.3757326197
Short name T31
Test name
Test status
Simulation time 226471103 ps
CPU time 11.05 seconds
Started Aug 09 07:16:27 PM PDT 24
Finished Aug 09 07:16:38 PM PDT 24
Peak memory 199832 kb
Host smart-54413baf-e427-4e59-a813-bc317c7980da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757326197 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.3757326197
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.1378192367
Short name T283
Test name
Test status
Simulation time 17105799029 ps
CPU time 779.67 seconds
Started Aug 09 07:16:31 PM PDT 24
Finished Aug 09 07:29:30 PM PDT 24
Peak memory 729728 kb
Host smart-f7bcdf9b-66ba-4aea-bc7c-a35db07e2558
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1378192367 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.1378192367
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.994045284
Short name T371
Test name
Test status
Simulation time 13233472280 ps
CPU time 189.51 seconds
Started Aug 09 07:16:27 PM PDT 24
Finished Aug 09 07:19:37 PM PDT 24
Peak memory 199828 kb
Host smart-a7a952e1-f5dc-4adb-a3ca-70575b98a715
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994045284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.994045284
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.3788205806
Short name T232
Test name
Test status
Simulation time 2576323747 ps
CPU time 8.12 seconds
Started Aug 09 07:16:24 PM PDT 24
Finished Aug 09 07:16:32 PM PDT 24
Peak memory 199880 kb
Host smart-09ed6f94-9f5d-4eec-8883-2f1891a2496c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788205806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.3788205806
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.1473818851
Short name T188
Test name
Test status
Simulation time 1814706665 ps
CPU time 15.66 seconds
Started Aug 09 07:16:23 PM PDT 24
Finished Aug 09 07:16:39 PM PDT 24
Peak memory 199884 kb
Host smart-f8c625fa-d5eb-4207-856b-3c0bef3ca716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473818851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.1473818851
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.3198618519
Short name T375
Test name
Test status
Simulation time 295750139436 ps
CPU time 3083.99 seconds
Started Aug 09 07:16:30 PM PDT 24
Finished Aug 09 08:07:55 PM PDT 24
Peak memory 781920 kb
Host smart-6ecf446d-f3e1-40ed-b4f4-1b49e11d5d4c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198618519 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.3198618519
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.212849074
Short name T123
Test name
Test status
Simulation time 11841348503 ps
CPU time 131.47 seconds
Started Aug 09 07:16:29 PM PDT 24
Finished Aug 09 07:18:41 PM PDT 24
Peak memory 199864 kb
Host smart-a8d783cd-f72c-4f26-918a-cf77caa25cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212849074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.212849074
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.4142540873
Short name T414
Test name
Test status
Simulation time 40553607 ps
CPU time 0.58 seconds
Started Aug 09 07:16:29 PM PDT 24
Finished Aug 09 07:16:30 PM PDT 24
Peak memory 195892 kb
Host smart-6a2324d5-46f6-46ae-8603-d78bd3df76f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142540873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.4142540873
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.739318321
Short name T515
Test name
Test status
Simulation time 531331000 ps
CPU time 29.77 seconds
Started Aug 09 07:16:34 PM PDT 24
Finished Aug 09 07:17:04 PM PDT 24
Peak memory 199780 kb
Host smart-10ef4d0e-1ad9-42c4-a049-0dc2dd2e60b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=739318321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.739318321
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.979381178
Short name T197
Test name
Test status
Simulation time 6056734983 ps
CPU time 48.77 seconds
Started Aug 09 07:16:30 PM PDT 24
Finished Aug 09 07:17:19 PM PDT 24
Peak memory 199888 kb
Host smart-94f39eed-aa4e-4c4f-9582-61c42c732b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979381178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.979381178
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.1093380838
Short name T171
Test name
Test status
Simulation time 4070530876 ps
CPU time 737.68 seconds
Started Aug 09 07:16:32 PM PDT 24
Finished Aug 09 07:28:50 PM PDT 24
Peak memory 725400 kb
Host smart-6bd4a1dd-645d-44dd-9c65-528487069814
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1093380838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.1093380838
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.3746077906
Short name T15
Test name
Test status
Simulation time 6099322437 ps
CPU time 84.77 seconds
Started Aug 09 07:16:30 PM PDT 24
Finished Aug 09 07:17:54 PM PDT 24
Peak memory 200116 kb
Host smart-10c8b243-ff9c-4a6e-92c5-1e4bff08dbe0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746077906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.3746077906
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.2415405966
Short name T516
Test name
Test status
Simulation time 5889218947 ps
CPU time 105.79 seconds
Started Aug 09 07:16:27 PM PDT 24
Finished Aug 09 07:18:12 PM PDT 24
Peak memory 216332 kb
Host smart-27bfe69d-2ad9-4a07-a0a6-82f70dd229a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415405966 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.2415405966
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.583813421
Short name T136
Test name
Test status
Simulation time 626129163 ps
CPU time 14.5 seconds
Started Aug 09 07:16:32 PM PDT 24
Finished Aug 09 07:16:46 PM PDT 24
Peak memory 199884 kb
Host smart-eee4878f-71e9-43e9-8297-3b0e1be4e019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583813421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.583813421
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.1649527014
Short name T34
Test name
Test status
Simulation time 34479709356 ps
CPU time 923.83 seconds
Started Aug 09 07:16:30 PM PDT 24
Finished Aug 09 07:31:54 PM PDT 24
Peak memory 687068 kb
Host smart-fa24b84a-25b9-4fce-9102-f3f02fcc007b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649527014 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.1649527014
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.1866446339
Short name T463
Test name
Test status
Simulation time 2326511402 ps
CPU time 114.55 seconds
Started Aug 09 07:16:26 PM PDT 24
Finished Aug 09 07:18:21 PM PDT 24
Peak memory 199836 kb
Host smart-10dfde4e-6a2c-4d5e-9920-ef5869811fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866446339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.1866446339
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.121402654
Short name T344
Test name
Test status
Simulation time 12268448 ps
CPU time 0.59 seconds
Started Aug 09 07:16:36 PM PDT 24
Finished Aug 09 07:16:37 PM PDT 24
Peak memory 195524 kb
Host smart-1b3195ef-5bf3-4670-8c4d-de8ab7a180b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121402654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.121402654
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.991411955
Short name T355
Test name
Test status
Simulation time 1255525926 ps
CPU time 71.57 seconds
Started Aug 09 07:16:41 PM PDT 24
Finished Aug 09 07:17:53 PM PDT 24
Peak memory 199744 kb
Host smart-92cfa1f7-d6f6-4fcb-9e7f-45630583d221
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=991411955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.991411955
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.802515990
Short name T144
Test name
Test status
Simulation time 2504140956 ps
CPU time 57.29 seconds
Started Aug 09 07:16:33 PM PDT 24
Finished Aug 09 07:17:30 PM PDT 24
Peak memory 199928 kb
Host smart-e4a05e21-68db-433d-9c3a-612531305074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802515990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.802515990
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.3850564674
Short name T164
Test name
Test status
Simulation time 4945370979 ps
CPU time 827.41 seconds
Started Aug 09 07:16:33 PM PDT 24
Finished Aug 09 07:30:20 PM PDT 24
Peak memory 698408 kb
Host smart-cc1ef7a4-2831-4a1b-8061-f1f1d95275e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3850564674 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.3850564674
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.1478252980
Short name T428
Test name
Test status
Simulation time 449960022 ps
CPU time 24.94 seconds
Started Aug 09 07:16:26 PM PDT 24
Finished Aug 09 07:16:51 PM PDT 24
Peak memory 199840 kb
Host smart-a8ff7fc9-ba93-419b-ab14-b17656bd52da
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478252980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.1478252980
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.2480148791
Short name T519
Test name
Test status
Simulation time 4102122528 ps
CPU time 74.42 seconds
Started Aug 09 07:16:33 PM PDT 24
Finished Aug 09 07:17:48 PM PDT 24
Peak memory 199908 kb
Host smart-f8791c38-3ccd-4a88-8231-c5fa0869c192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480148791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.2480148791
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.292697518
Short name T465
Test name
Test status
Simulation time 736127577 ps
CPU time 6.37 seconds
Started Aug 09 07:16:31 PM PDT 24
Finished Aug 09 07:16:37 PM PDT 24
Peak memory 199848 kb
Host smart-09acebad-9ac1-470a-9c6d-22ded1c59a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292697518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.292697518
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.564266526
Short name T236
Test name
Test status
Simulation time 11420819374 ps
CPU time 210.2 seconds
Started Aug 09 07:16:30 PM PDT 24
Finished Aug 09 07:20:00 PM PDT 24
Peak memory 232152 kb
Host smart-1147ea76-3887-4935-9987-6e3071203649
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564266526 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.564266526
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.1802144934
Short name T473
Test name
Test status
Simulation time 5718640815 ps
CPU time 91.93 seconds
Started Aug 09 07:16:33 PM PDT 24
Finished Aug 09 07:18:05 PM PDT 24
Peak memory 199916 kb
Host smart-dde862f4-431a-4dae-9bda-82ad8b8b3db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802144934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.1802144934
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.2121791117
Short name T237
Test name
Test status
Simulation time 12537265 ps
CPU time 0.61 seconds
Started Aug 09 07:16:35 PM PDT 24
Finished Aug 09 07:16:36 PM PDT 24
Peak memory 195928 kb
Host smart-f6b0dadc-014a-46c0-aeaa-97deb5485b1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121791117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.2121791117
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.3010728890
Short name T323
Test name
Test status
Simulation time 2370440435 ps
CPU time 33.37 seconds
Started Aug 09 07:16:33 PM PDT 24
Finished Aug 09 07:17:06 PM PDT 24
Peak memory 199924 kb
Host smart-9ddaba1f-7d7e-4b60-9add-61df7172e078
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3010728890 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.3010728890
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.3978237883
Short name T437
Test name
Test status
Simulation time 5584712054 ps
CPU time 49.65 seconds
Started Aug 09 07:16:33 PM PDT 24
Finished Aug 09 07:17:23 PM PDT 24
Peak memory 199924 kb
Host smart-60ac224b-aa05-4738-a59c-072427b4c356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978237883 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.3978237883
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.215890754
Short name T168
Test name
Test status
Simulation time 10595535654 ps
CPU time 980.51 seconds
Started Aug 09 07:16:31 PM PDT 24
Finished Aug 09 07:32:52 PM PDT 24
Peak memory 740552 kb
Host smart-7c671948-5397-47eb-8bc6-3549d61d7105
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=215890754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.215890754
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.1362214750
Short name T14
Test name
Test status
Simulation time 3173513513 ps
CPU time 76.09 seconds
Started Aug 09 07:16:32 PM PDT 24
Finished Aug 09 07:17:48 PM PDT 24
Peak memory 199888 kb
Host smart-bef16b86-42fc-4d0b-93af-8cfca506e411
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362214750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.1362214750
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.3191378129
Short name T345
Test name
Test status
Simulation time 34196882847 ps
CPU time 135.15 seconds
Started Aug 09 07:16:38 PM PDT 24
Finished Aug 09 07:18:53 PM PDT 24
Peak memory 199916 kb
Host smart-c4bce657-c4f7-4213-8a8e-248dd2d67fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191378129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.3191378129
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.218006653
Short name T468
Test name
Test status
Simulation time 176843544 ps
CPU time 8.38 seconds
Started Aug 09 07:16:30 PM PDT 24
Finished Aug 09 07:16:39 PM PDT 24
Peak memory 199780 kb
Host smart-2953df27-1343-4d33-a4ba-fc41e0cb556e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218006653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.218006653
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.3645027264
Short name T175
Test name
Test status
Simulation time 12569939570 ps
CPU time 29.39 seconds
Started Aug 09 07:16:34 PM PDT 24
Finished Aug 09 07:17:03 PM PDT 24
Peak memory 199916 kb
Host smart-bd72f238-1452-4253-8c68-71c49d7eccfd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645027264 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.3645027264
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.1328359817
Short name T356
Test name
Test status
Simulation time 7283676307 ps
CPU time 90.1 seconds
Started Aug 09 07:16:36 PM PDT 24
Finished Aug 09 07:18:06 PM PDT 24
Peak memory 199884 kb
Host smart-425256e6-c7b7-4cc2-b883-0b84b910fdea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328359817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.1328359817
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.2774705427
Short name T154
Test name
Test status
Simulation time 41626073 ps
CPU time 0.59 seconds
Started Aug 09 07:16:35 PM PDT 24
Finished Aug 09 07:16:35 PM PDT 24
Peak memory 195940 kb
Host smart-e6fb72c1-bd86-4a5a-b9aa-f09332acbf6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774705427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.2774705427
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.2653238179
Short name T524
Test name
Test status
Simulation time 6655067146 ps
CPU time 47.99 seconds
Started Aug 09 07:16:35 PM PDT 24
Finished Aug 09 07:17:23 PM PDT 24
Peak memory 199840 kb
Host smart-0e613aa7-5956-420e-ad84-212ecd538dcd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2653238179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.2653238179
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.1208726897
Short name T504
Test name
Test status
Simulation time 6546609049 ps
CPU time 41.02 seconds
Started Aug 09 07:16:40 PM PDT 24
Finished Aug 09 07:17:21 PM PDT 24
Peak memory 199916 kb
Host smart-852aa916-e1fa-4da4-8f2b-94111bdd44f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208726897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.1208726897
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.1405536683
Short name T386
Test name
Test status
Simulation time 31056920552 ps
CPU time 834.35 seconds
Started Aug 09 07:16:33 PM PDT 24
Finished Aug 09 07:30:28 PM PDT 24
Peak memory 726888 kb
Host smart-cf325be9-ebdf-4e96-ab5e-752f899b6ce3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1405536683 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.1405536683
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.1796889954
Short name T423
Test name
Test status
Simulation time 19777132773 ps
CPU time 36.51 seconds
Started Aug 09 07:16:38 PM PDT 24
Finished Aug 09 07:17:15 PM PDT 24
Peak memory 199828 kb
Host smart-c0da7e8c-7e2c-45fc-88fd-952b40d3b367
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796889954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.1796889954
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.1349234517
Short name T441
Test name
Test status
Simulation time 10556462773 ps
CPU time 140.85 seconds
Started Aug 09 07:16:33 PM PDT 24
Finished Aug 09 07:18:54 PM PDT 24
Peak memory 199968 kb
Host smart-d33d0a67-ac08-4b1e-b5f6-52a8023e3e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349234517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.1349234517
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.3585037717
Short name T407
Test name
Test status
Simulation time 1054500885 ps
CPU time 12.52 seconds
Started Aug 09 07:16:40 PM PDT 24
Finished Aug 09 07:16:53 PM PDT 24
Peak memory 199760 kb
Host smart-76db5306-85c9-439a-8997-99f5b47a59c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585037717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.3585037717
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.3556935945
Short name T439
Test name
Test status
Simulation time 7200811401 ps
CPU time 124.59 seconds
Started Aug 09 07:16:44 PM PDT 24
Finished Aug 09 07:18:49 PM PDT 24
Peak memory 216312 kb
Host smart-664e8645-9816-40b2-996f-ed6fab9e4ad9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556935945 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.3556935945
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.1152103117
Short name T394
Test name
Test status
Simulation time 17092854173 ps
CPU time 58.09 seconds
Started Aug 09 07:16:36 PM PDT 24
Finished Aug 09 07:17:34 PM PDT 24
Peak memory 199908 kb
Host smart-215260b4-5d42-4dc0-8651-01ddec4e079c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152103117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.1152103117
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.3775650350
Short name T448
Test name
Test status
Simulation time 13420491 ps
CPU time 0.57 seconds
Started Aug 09 07:16:34 PM PDT 24
Finished Aug 09 07:16:34 PM PDT 24
Peak memory 194920 kb
Host smart-0a0ee77e-e4e4-4c16-b71a-1defba969971
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775650350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.3775650350
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.2606173980
Short name T193
Test name
Test status
Simulation time 1960581160 ps
CPU time 32 seconds
Started Aug 09 07:16:40 PM PDT 24
Finished Aug 09 07:17:12 PM PDT 24
Peak memory 199832 kb
Host smart-099b6e30-e5df-45b0-83e6-7e50dd324ff9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2606173980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.2606173980
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.3471252980
Short name T405
Test name
Test status
Simulation time 8293341929 ps
CPU time 37.39 seconds
Started Aug 09 07:16:38 PM PDT 24
Finished Aug 09 07:17:15 PM PDT 24
Peak memory 199984 kb
Host smart-4f024904-82d0-4201-9e84-27cc7fde8790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471252980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.3471252980
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.2289976978
Short name T392
Test name
Test status
Simulation time 3237778580 ps
CPU time 515.35 seconds
Started Aug 09 07:16:34 PM PDT 24
Finished Aug 09 07:25:09 PM PDT 24
Peak memory 482548 kb
Host smart-9a4dbe8c-2570-438b-960c-3d4f89913b95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2289976978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.2289976978
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.4277170031
Short name T270
Test name
Test status
Simulation time 54191038208 ps
CPU time 115.22 seconds
Started Aug 09 07:16:33 PM PDT 24
Finished Aug 09 07:18:28 PM PDT 24
Peak memory 199880 kb
Host smart-5889d623-e892-4f65-9554-d67306d3143d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277170031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.4277170031
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.922508370
Short name T32
Test name
Test status
Simulation time 4553472972 ps
CPU time 73.42 seconds
Started Aug 09 07:16:36 PM PDT 24
Finished Aug 09 07:17:49 PM PDT 24
Peak memory 199884 kb
Host smart-7df9483b-5ae8-4b5f-b79b-c9870dff349a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922508370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.922508370
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.1631078867
Short name T526
Test name
Test status
Simulation time 3216150142 ps
CPU time 13.33 seconds
Started Aug 09 07:16:33 PM PDT 24
Finished Aug 09 07:16:46 PM PDT 24
Peak memory 199896 kb
Host smart-797803f9-625f-41db-ac4d-f2dedb659737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631078867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.1631078867
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.334443700
Short name T279
Test name
Test status
Simulation time 31771779231 ps
CPU time 472.9 seconds
Started Aug 09 07:16:35 PM PDT 24
Finished Aug 09 07:24:28 PM PDT 24
Peak memory 199944 kb
Host smart-0067a6ff-0539-4da6-8bfb-746318ec2245
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334443700 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.334443700
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.2697810629
Short name T357
Test name
Test status
Simulation time 5648025737 ps
CPU time 107.52 seconds
Started Aug 09 07:16:39 PM PDT 24
Finished Aug 09 07:18:26 PM PDT 24
Peak memory 200104 kb
Host smart-311f3cbd-16bf-4521-898e-2eba389b3acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697810629 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.2697810629
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.108391091
Short name T244
Test name
Test status
Simulation time 19356505 ps
CPU time 0.55 seconds
Started Aug 09 07:16:00 PM PDT 24
Finished Aug 09 07:16:01 PM PDT 24
Peak memory 194920 kb
Host smart-a26a04ae-27e7-4ec1-9bd7-3756b0ec0fee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108391091 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.108391091
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.4144695233
Short name T457
Test name
Test status
Simulation time 602443235 ps
CPU time 32.63 seconds
Started Aug 09 07:16:02 PM PDT 24
Finished Aug 09 07:16:35 PM PDT 24
Peak memory 199788 kb
Host smart-c69001c2-1d40-4e52-8027-659a463038c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4144695233 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.4144695233
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.940101964
Short name T235
Test name
Test status
Simulation time 1135121803 ps
CPU time 21.56 seconds
Started Aug 09 07:16:02 PM PDT 24
Finished Aug 09 07:16:24 PM PDT 24
Peak memory 199792 kb
Host smart-5014b939-32bd-4a42-a362-cf36a72a84ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940101964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.940101964
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.3845911301
Short name T255
Test name
Test status
Simulation time 1732221943 ps
CPU time 120.88 seconds
Started Aug 09 07:16:11 PM PDT 24
Finished Aug 09 07:18:12 PM PDT 24
Peak memory 367488 kb
Host smart-07f30ed4-6c8e-486c-a70f-e6b09ae76c03
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3845911301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.3845911301
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.4198521892
Short name T362
Test name
Test status
Simulation time 10605365949 ps
CPU time 46.54 seconds
Started Aug 09 07:16:00 PM PDT 24
Finished Aug 09 07:16:47 PM PDT 24
Peak memory 199888 kb
Host smart-1ffd010b-d6c0-4652-bdf7-190fbd0069e7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198521892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.4198521892
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.408339428
Short name T2
Test name
Test status
Simulation time 1784247059 ps
CPU time 101.77 seconds
Started Aug 09 07:16:01 PM PDT 24
Finished Aug 09 07:17:43 PM PDT 24
Peak memory 199852 kb
Host smart-16a3b711-86f0-41e4-8884-5a7eff42dbf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408339428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.408339428
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_smoke.143275753
Short name T90
Test name
Test status
Simulation time 114672886 ps
CPU time 5.36 seconds
Started Aug 09 07:16:16 PM PDT 24
Finished Aug 09 07:16:22 PM PDT 24
Peak memory 199832 kb
Host smart-cbeb77c1-50bb-49da-9060-c3a061c4092c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143275753 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.143275753
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.2488730028
Short name T76
Test name
Test status
Simulation time 12247744487 ps
CPU time 1037.5 seconds
Started Aug 09 07:16:01 PM PDT 24
Finished Aug 09 07:33:19 PM PDT 24
Peak memory 695924 kb
Host smart-0a34bd61-87cc-45ac-8944-31c5ff717cfd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488730028 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.2488730028
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_stress_all_with_rand_reset.3714329199
Short name T13
Test name
Test status
Simulation time 133834718262 ps
CPU time 2403.78 seconds
Started Aug 09 07:16:06 PM PDT 24
Finished Aug 09 07:56:10 PM PDT 24
Peak memory 662368 kb
Host smart-c41b99bd-d197-4d8c-a6c6-09b0eb077c7d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3714329199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all_with_rand_reset.3714329199
Directory /workspace/2.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_test_hmac256_vectors.631822149
Short name T402
Test name
Test status
Simulation time 6056018313 ps
CPU time 52.73 seconds
Started Aug 09 07:16:06 PM PDT 24
Finished Aug 09 07:16:58 PM PDT 24
Peak memory 199880 kb
Host smart-b45ae248-301a-43f3-b4cf-daa862c8142b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=631822149 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac256_vectors.631822149
Directory /workspace/2.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac384_vectors.951372389
Short name T30
Test name
Test status
Simulation time 2327193905 ps
CPU time 84.99 seconds
Started Aug 09 07:16:06 PM PDT 24
Finished Aug 09 07:17:31 PM PDT 24
Peak memory 199872 kb
Host smart-7fca81d6-d339-4748-97b3-a1e224d5704a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=951372389 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac384_vectors.951372389
Directory /workspace/2.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac512_vectors.244784208
Short name T310
Test name
Test status
Simulation time 20018485860 ps
CPU time 73.87 seconds
Started Aug 09 07:16:02 PM PDT 24
Finished Aug 09 07:17:16 PM PDT 24
Peak memory 199840 kb
Host smart-ee501573-7c33-4420-b028-bf29c0d5e00c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=244784208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac512_vectors.244784208
Directory /workspace/2.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha256_vectors.851858717
Short name T509
Test name
Test status
Simulation time 37496815803 ps
CPU time 638.12 seconds
Started Aug 09 07:16:02 PM PDT 24
Finished Aug 09 07:26:41 PM PDT 24
Peak memory 199840 kb
Host smart-15925ebb-03b9-4e2a-8c67-3f06ec7b1c2f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=851858717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha256_vectors.851858717
Directory /workspace/2.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha384_vectors.1913440199
Short name T281
Test name
Test status
Simulation time 39060636516 ps
CPU time 2283.05 seconds
Started Aug 09 07:16:12 PM PDT 24
Finished Aug 09 07:54:15 PM PDT 24
Peak memory 215404 kb
Host smart-e1190726-cf73-436b-9229-a28fc8367631
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1913440199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha384_vectors.1913440199
Directory /workspace/2.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha512_vectors.3566140100
Short name T471
Test name
Test status
Simulation time 547856572889 ps
CPU time 2436.7 seconds
Started Aug 09 07:16:11 PM PDT 24
Finished Aug 09 07:56:48 PM PDT 24
Peak memory 215396 kb
Host smart-9a6f0d90-aeb6-4050-a74d-bc8eaa8fcc46
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3566140100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha512_vectors.3566140100
Directory /workspace/2.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.1835027653
Short name T145
Test name
Test status
Simulation time 285323973 ps
CPU time 3.91 seconds
Started Aug 09 07:16:11 PM PDT 24
Finished Aug 09 07:16:15 PM PDT 24
Peak memory 199728 kb
Host smart-eb42f481-5dca-4524-ae57-ecd8b1d080d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835027653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.1835027653
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.1041743994
Short name T322
Test name
Test status
Simulation time 11114534 ps
CPU time 0.59 seconds
Started Aug 09 07:16:52 PM PDT 24
Finished Aug 09 07:16:53 PM PDT 24
Peak memory 196600 kb
Host smart-49131d04-b04a-4f31-9bf2-350b427fbf53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041743994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.1041743994
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.2798532776
Short name T530
Test name
Test status
Simulation time 3756004924 ps
CPU time 46.43 seconds
Started Aug 09 07:16:48 PM PDT 24
Finished Aug 09 07:17:34 PM PDT 24
Peak memory 199868 kb
Host smart-835ab734-4cce-4275-8275-671ea3541c55
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2798532776 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.2798532776
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.3449029484
Short name T444
Test name
Test status
Simulation time 1241168676 ps
CPU time 9.89 seconds
Started Aug 09 07:16:38 PM PDT 24
Finished Aug 09 07:16:48 PM PDT 24
Peak memory 199832 kb
Host smart-29b0c6b5-66c0-4917-af65-66fbf66ebc85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449029484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.3449029484
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.2596586840
Short name T49
Test name
Test status
Simulation time 8391437468 ps
CPU time 1819.1 seconds
Started Aug 09 07:16:37 PM PDT 24
Finished Aug 09 07:47:02 PM PDT 24
Peak memory 751048 kb
Host smart-10a84c87-5faa-4e52-8455-005fb1aa1202
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2596586840 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.2596586840
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.2909347428
Short name T60
Test name
Test status
Simulation time 7528079824 ps
CPU time 134.56 seconds
Started Aug 09 07:16:34 PM PDT 24
Finished Aug 09 07:18:49 PM PDT 24
Peak memory 199952 kb
Host smart-da7580ea-abe9-4841-9e85-7f7ff49275b3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909347428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.2909347428
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.3090501697
Short name T210
Test name
Test status
Simulation time 30837139 ps
CPU time 0.65 seconds
Started Aug 09 07:16:48 PM PDT 24
Finished Aug 09 07:16:49 PM PDT 24
Peak memory 196436 kb
Host smart-e373f97d-9279-49a2-8310-9d38efc22a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090501697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.3090501697
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.1165625132
Short name T411
Test name
Test status
Simulation time 290661166 ps
CPU time 12.55 seconds
Started Aug 09 07:16:37 PM PDT 24
Finished Aug 09 07:16:49 PM PDT 24
Peak memory 199884 kb
Host smart-c68b5790-440f-4e85-b7cb-c4b8ba801567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165625132 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.1165625132
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.1935151863
Short name T469
Test name
Test status
Simulation time 27920696812 ps
CPU time 356.89 seconds
Started Aug 09 07:16:35 PM PDT 24
Finished Aug 09 07:22:32 PM PDT 24
Peak memory 216272 kb
Host smart-437b506b-e5f3-4cd8-abf7-526d537c719f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935151863 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.1935151863
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.2407602401
Short name T379
Test name
Test status
Simulation time 20884063834 ps
CPU time 72.16 seconds
Started Aug 09 07:16:32 PM PDT 24
Finished Aug 09 07:17:44 PM PDT 24
Peak memory 199876 kb
Host smart-240e2dba-d295-46f4-9920-3b896a962158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407602401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.2407602401
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.3978573950
Short name T493
Test name
Test status
Simulation time 45083501 ps
CPU time 0.6 seconds
Started Aug 09 07:16:39 PM PDT 24
Finished Aug 09 07:16:40 PM PDT 24
Peak memory 195620 kb
Host smart-35d28cdc-64cd-4c5c-8f2c-fcd80bad53ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978573950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.3978573950
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.3967084893
Short name T479
Test name
Test status
Simulation time 483360008 ps
CPU time 28.29 seconds
Started Aug 09 07:16:46 PM PDT 24
Finished Aug 09 07:17:14 PM PDT 24
Peak memory 199768 kb
Host smart-ccb28f52-0a8d-4c02-88de-9f5c35208960
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3967084893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.3967084893
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.2437343144
Short name T224
Test name
Test status
Simulation time 1235324151 ps
CPU time 8.17 seconds
Started Aug 09 07:16:35 PM PDT 24
Finished Aug 09 07:16:44 PM PDT 24
Peak memory 199756 kb
Host smart-8493768f-35c5-4e2b-a0a3-ba679a9a168f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437343144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.2437343144
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.3318571564
Short name T383
Test name
Test status
Simulation time 28846856741 ps
CPU time 741.39 seconds
Started Aug 09 07:16:40 PM PDT 24
Finished Aug 09 07:29:02 PM PDT 24
Peak memory 717612 kb
Host smart-b7a11ec2-a7ef-429a-84e9-c4c2fda5a5ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3318571564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.3318571564
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.2194777657
Short name T452
Test name
Test status
Simulation time 12432223472 ps
CPU time 180.22 seconds
Started Aug 09 07:16:45 PM PDT 24
Finished Aug 09 07:19:46 PM PDT 24
Peak memory 199860 kb
Host smart-0bdcb41f-0c15-42ea-8db2-4335e11bc67c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194777657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.2194777657
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.531734875
Short name T222
Test name
Test status
Simulation time 6325356502 ps
CPU time 44.34 seconds
Started Aug 09 07:16:41 PM PDT 24
Finished Aug 09 07:17:25 PM PDT 24
Peak memory 200120 kb
Host smart-e528ae59-e548-4f3b-81a3-0bbf22dd6412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531734875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.531734875
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.1372578960
Short name T251
Test name
Test status
Simulation time 2670937908 ps
CPU time 11.76 seconds
Started Aug 09 07:16:34 PM PDT 24
Finished Aug 09 07:16:46 PM PDT 24
Peak memory 199884 kb
Host smart-80a61e35-257f-4c00-a7c9-8811e8ac937e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372578960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.1372578960
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.1953936073
Short name T296
Test name
Test status
Simulation time 93894252483 ps
CPU time 2251.54 seconds
Started Aug 09 07:16:41 PM PDT 24
Finished Aug 09 07:54:13 PM PDT 24
Peak memory 766084 kb
Host smart-69f0d5b7-518c-4ddf-be36-646b19f3a0c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953936073 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.1953936073
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.3691403777
Short name T506
Test name
Test status
Simulation time 31332750541 ps
CPU time 143.74 seconds
Started Aug 09 07:16:50 PM PDT 24
Finished Aug 09 07:19:14 PM PDT 24
Peak memory 199924 kb
Host smart-f40d78cf-6345-4ea6-8a4d-8c304b9fc45e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691403777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.3691403777
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.297679473
Short name T330
Test name
Test status
Simulation time 44053794 ps
CPU time 0.57 seconds
Started Aug 09 07:16:41 PM PDT 24
Finished Aug 09 07:16:42 PM PDT 24
Peak memory 195928 kb
Host smart-df06c043-d9f3-40c9-a109-9de7411ae042
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297679473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.297679473
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.305038730
Short name T396
Test name
Test status
Simulation time 778590121 ps
CPU time 42.65 seconds
Started Aug 09 07:16:45 PM PDT 24
Finished Aug 09 07:17:28 PM PDT 24
Peak memory 199776 kb
Host smart-dbb46996-467e-46d7-bcb6-e14b5d681dcc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=305038730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.305038730
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.3805251157
Short name T406
Test name
Test status
Simulation time 568290087 ps
CPU time 30.1 seconds
Started Aug 09 07:16:38 PM PDT 24
Finished Aug 09 07:17:08 PM PDT 24
Peak memory 200060 kb
Host smart-0627c3a0-4b6a-4b9f-88ec-6a0b2bda7365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805251157 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.3805251157
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.1163273756
Short name T365
Test name
Test status
Simulation time 6958296375 ps
CPU time 1225.35 seconds
Started Aug 09 07:16:41 PM PDT 24
Finished Aug 09 07:37:07 PM PDT 24
Peak memory 756308 kb
Host smart-ed8bc587-32ed-4f36-ab00-dd92e402a304
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1163273756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.1163273756
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.2517736277
Short name T79
Test name
Test status
Simulation time 6084864265 ps
CPU time 72.85 seconds
Started Aug 09 07:16:39 PM PDT 24
Finished Aug 09 07:17:52 PM PDT 24
Peak memory 199828 kb
Host smart-09c94ef3-9792-47af-b6ff-34624ab59aa1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517736277 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.2517736277
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.167704195
Short name T320
Test name
Test status
Simulation time 6958016170 ps
CPU time 191.53 seconds
Started Aug 09 07:16:38 PM PDT 24
Finished Aug 09 07:19:49 PM PDT 24
Peak memory 199968 kb
Host smart-4f7ede86-debc-4c82-8589-8bce369d20c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167704195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.167704195
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.4174697749
Short name T217
Test name
Test status
Simulation time 127934026 ps
CPU time 1.26 seconds
Started Aug 09 07:16:40 PM PDT 24
Finished Aug 09 07:16:42 PM PDT 24
Peak memory 199800 kb
Host smart-e1988541-5bda-4561-9719-fe5311826487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174697749 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.4174697749
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.202294753
Short name T226
Test name
Test status
Simulation time 216204800293 ps
CPU time 391.38 seconds
Started Aug 09 07:16:38 PM PDT 24
Finished Aug 09 07:23:10 PM PDT 24
Peak memory 199908 kb
Host smart-966f7a5e-7150-4f77-b596-5f53bdf6a1eb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202294753 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.202294753
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.3207815500
Short name T122
Test name
Test status
Simulation time 2076757675 ps
CPU time 82.68 seconds
Started Aug 09 07:16:52 PM PDT 24
Finished Aug 09 07:18:14 PM PDT 24
Peak memory 199848 kb
Host smart-749ef288-b10d-4bd2-aaad-73c5e01bac81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207815500 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.3207815500
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.470103643
Short name T41
Test name
Test status
Simulation time 44601858 ps
CPU time 0.63 seconds
Started Aug 09 07:16:43 PM PDT 24
Finished Aug 09 07:16:44 PM PDT 24
Peak memory 195940 kb
Host smart-852dd7cf-dd70-42a0-9387-452729a05a33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470103643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.470103643
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.4129156901
Short name T435
Test name
Test status
Simulation time 7895954045 ps
CPU time 97.88 seconds
Started Aug 09 07:16:49 PM PDT 24
Finished Aug 09 07:18:27 PM PDT 24
Peak memory 199888 kb
Host smart-31f82f02-38b7-4376-b32f-159d8a82a796
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4129156901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.4129156901
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.3612691774
Short name T38
Test name
Test status
Simulation time 16275380318 ps
CPU time 50.4 seconds
Started Aug 09 07:16:40 PM PDT 24
Finished Aug 09 07:17:31 PM PDT 24
Peak memory 208120 kb
Host smart-da347f1b-1338-4148-aec8-14d00a45365b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612691774 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.3612691774
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.449879813
Short name T393
Test name
Test status
Simulation time 5353608345 ps
CPU time 1071.01 seconds
Started Aug 09 07:16:44 PM PDT 24
Finished Aug 09 07:34:35 PM PDT 24
Peak memory 735364 kb
Host smart-8de5c778-ac0c-4e6c-a6b1-fe0b2d7a5937
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=449879813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.449879813
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.1853843921
Short name T294
Test name
Test status
Simulation time 17670256408 ps
CPU time 55.07 seconds
Started Aug 09 07:16:41 PM PDT 24
Finished Aug 09 07:17:36 PM PDT 24
Peak memory 199800 kb
Host smart-5ef29d61-bdd9-4304-9a5a-31c585dece31
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853843921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.1853843921
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.1990139939
Short name T382
Test name
Test status
Simulation time 325862994 ps
CPU time 19.15 seconds
Started Aug 09 07:16:38 PM PDT 24
Finished Aug 09 07:16:57 PM PDT 24
Peak memory 199832 kb
Host smart-ec7bbcaf-e2e4-4001-b164-fbc5d0c84f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990139939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.1990139939
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.4055894939
Short name T290
Test name
Test status
Simulation time 127110401 ps
CPU time 5.99 seconds
Started Aug 09 07:16:48 PM PDT 24
Finished Aug 09 07:16:54 PM PDT 24
Peak memory 199900 kb
Host smart-364ab3be-857f-48f5-a428-d3ff0bb3cd97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055894939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.4055894939
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.4058241056
Short name T124
Test name
Test status
Simulation time 189401970919 ps
CPU time 2001.5 seconds
Started Aug 09 07:16:45 PM PDT 24
Finished Aug 09 07:50:07 PM PDT 24
Peak memory 747200 kb
Host smart-04c45b04-a9e0-4659-86b4-3097f861a47a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058241056 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.4058241056
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.4117315654
Short name T485
Test name
Test status
Simulation time 24414932349 ps
CPU time 102.35 seconds
Started Aug 09 07:16:41 PM PDT 24
Finished Aug 09 07:18:24 PM PDT 24
Peak memory 199896 kb
Host smart-5df2d8e4-a852-4961-a155-949295da627c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117315654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.4117315654
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.3543224661
Short name T505
Test name
Test status
Simulation time 30030706 ps
CPU time 0.59 seconds
Started Aug 09 07:16:44 PM PDT 24
Finished Aug 09 07:16:44 PM PDT 24
Peak memory 195564 kb
Host smart-a9fa58ab-edc6-4aed-b23b-7cdf5a888767
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543224661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.3543224661
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.2600819792
Short name T229
Test name
Test status
Simulation time 731345925 ps
CPU time 21.66 seconds
Started Aug 09 07:16:35 PM PDT 24
Finished Aug 09 07:16:57 PM PDT 24
Peak memory 199852 kb
Host smart-d1aaadd5-caf9-4c61-a122-b53b1d876d1f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2600819792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.2600819792
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.3748595662
Short name T156
Test name
Test status
Simulation time 5162880516 ps
CPU time 18.27 seconds
Started Aug 09 07:16:36 PM PDT 24
Finished Aug 09 07:16:54 PM PDT 24
Peak memory 199916 kb
Host smart-6e4f663c-3fca-406e-abbb-4eed9c596312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748595662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.3748595662
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_error.1068553442
Short name T80
Test name
Test status
Simulation time 43359722062 ps
CPU time 139.89 seconds
Started Aug 09 07:16:44 PM PDT 24
Finished Aug 09 07:19:04 PM PDT 24
Peak memory 199864 kb
Host smart-99c7adfa-20cf-4ce4-a28a-43f60620e6a4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068553442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.1068553442
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.1121137094
Short name T455
Test name
Test status
Simulation time 11218642068 ps
CPU time 141.69 seconds
Started Aug 09 07:16:44 PM PDT 24
Finished Aug 09 07:19:06 PM PDT 24
Peak memory 199880 kb
Host smart-20dc7eec-4fda-4863-8548-bebb4be051bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121137094 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.1121137094
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.2981089984
Short name T273
Test name
Test status
Simulation time 248563564 ps
CPU time 3.17 seconds
Started Aug 09 07:16:46 PM PDT 24
Finished Aug 09 07:16:49 PM PDT 24
Peak memory 199788 kb
Host smart-fc0b3f80-6752-4af1-b202-573bf64f6475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981089984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.2981089984
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.1915136379
Short name T401
Test name
Test status
Simulation time 13504474903 ps
CPU time 1974.6 seconds
Started Aug 09 07:16:38 PM PDT 24
Finished Aug 09 07:49:33 PM PDT 24
Peak memory 757696 kb
Host smart-0a86f665-63f4-438d-9828-f29b31f329f5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915136379 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.1915136379
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.3717518857
Short name T169
Test name
Test status
Simulation time 10010346895 ps
CPU time 102.82 seconds
Started Aug 09 07:16:41 PM PDT 24
Finished Aug 09 07:18:24 PM PDT 24
Peak memory 199932 kb
Host smart-681ef74c-ab56-46fa-b0c2-f116e1561616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717518857 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.3717518857
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.1256425123
Short name T194
Test name
Test status
Simulation time 14067713 ps
CPU time 0.6 seconds
Started Aug 09 07:16:44 PM PDT 24
Finished Aug 09 07:16:44 PM PDT 24
Peak memory 196652 kb
Host smart-901a330f-80bd-4216-9a4a-ee9f436b27e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256425123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.1256425123
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.2048706303
Short name T321
Test name
Test status
Simulation time 49959963 ps
CPU time 2.98 seconds
Started Aug 09 07:16:50 PM PDT 24
Finished Aug 09 07:16:53 PM PDT 24
Peak memory 199732 kb
Host smart-5d65448a-f9c1-4891-9482-05575a351099
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2048706303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.2048706303
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.3103610139
Short name T9
Test name
Test status
Simulation time 775692068 ps
CPU time 41.63 seconds
Started Aug 09 07:16:39 PM PDT 24
Finished Aug 09 07:17:21 PM PDT 24
Peak memory 199812 kb
Host smart-dcc164bc-3f70-4057-9a49-87760a3fe343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103610139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.3103610139
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.561470847
Short name T313
Test name
Test status
Simulation time 21544778230 ps
CPU time 1002.85 seconds
Started Aug 09 07:16:52 PM PDT 24
Finished Aug 09 07:33:35 PM PDT 24
Peak memory 738788 kb
Host smart-693bf501-85c3-4da4-b4fc-505333ca8fca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=561470847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.561470847
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.903622336
Short name T399
Test name
Test status
Simulation time 457743936 ps
CPU time 10.14 seconds
Started Aug 09 07:16:45 PM PDT 24
Finished Aug 09 07:16:55 PM PDT 24
Peak memory 199836 kb
Host smart-afb8de3c-b73e-4e57-a18c-7bd37ecec77a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903622336 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.903622336
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.1774164918
Short name T527
Test name
Test status
Simulation time 2619753587 ps
CPU time 151.48 seconds
Started Aug 09 07:16:48 PM PDT 24
Finished Aug 09 07:19:20 PM PDT 24
Peak memory 199932 kb
Host smart-87ffac44-e727-4559-a36f-e18e494217a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774164918 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.1774164918
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.1150130897
Short name T248
Test name
Test status
Simulation time 279242180 ps
CPU time 11.88 seconds
Started Aug 09 07:16:41 PM PDT 24
Finished Aug 09 07:16:53 PM PDT 24
Peak memory 199788 kb
Host smart-2e33547d-2554-4556-8ad0-bd7a54d86d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150130897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.1150130897
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.1800476499
Short name T476
Test name
Test status
Simulation time 12513679136 ps
CPU time 172.51 seconds
Started Aug 09 07:16:46 PM PDT 24
Finished Aug 09 07:19:38 PM PDT 24
Peak memory 216272 kb
Host smart-b49b7c6b-bf36-4075-94fc-0c944d21c2a8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800476499 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.1800476499
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.2240503039
Short name T388
Test name
Test status
Simulation time 3855849335 ps
CPU time 17.67 seconds
Started Aug 09 07:16:42 PM PDT 24
Finished Aug 09 07:17:00 PM PDT 24
Peak memory 199900 kb
Host smart-ff9c3e67-2f16-4ab2-91b5-d6b32d323d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240503039 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.2240503039
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.4256501373
Short name T186
Test name
Test status
Simulation time 18840578 ps
CPU time 0.59 seconds
Started Aug 09 07:16:48 PM PDT 24
Finished Aug 09 07:16:49 PM PDT 24
Peak memory 194896 kb
Host smart-123bf10b-f2cf-412b-aa1a-62ae37221c04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256501373 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.4256501373
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.4061715261
Short name T427
Test name
Test status
Simulation time 505956504 ps
CPU time 22.17 seconds
Started Aug 09 07:16:41 PM PDT 24
Finished Aug 09 07:17:03 PM PDT 24
Peak memory 199840 kb
Host smart-dd89eba9-4dbd-4518-9053-9a35ef887649
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4061715261 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.4061715261
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.4243063708
Short name T309
Test name
Test status
Simulation time 2324110989 ps
CPU time 29.66 seconds
Started Aug 09 07:16:39 PM PDT 24
Finished Aug 09 07:17:09 PM PDT 24
Peak memory 199924 kb
Host smart-fda7dbbf-3aeb-4c56-a298-8d431622a747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243063708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.4243063708
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.2910970848
Short name T487
Test name
Test status
Simulation time 1060237744 ps
CPU time 180.31 seconds
Started Aug 09 07:16:52 PM PDT 24
Finished Aug 09 07:19:53 PM PDT 24
Peak memory 572408 kb
Host smart-886145d4-8272-457d-8a63-2ec9f832243c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2910970848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.2910970848
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.4021294760
Short name T78
Test name
Test status
Simulation time 20208167279 ps
CPU time 125.53 seconds
Started Aug 09 07:16:44 PM PDT 24
Finished Aug 09 07:18:50 PM PDT 24
Peak memory 199880 kb
Host smart-b94eb2be-a993-4379-89cf-2a31bd736374
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021294760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.4021294760
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.3583870497
Short name T268
Test name
Test status
Simulation time 40846023934 ps
CPU time 169.01 seconds
Started Aug 09 07:16:48 PM PDT 24
Finished Aug 09 07:19:37 PM PDT 24
Peak memory 199856 kb
Host smart-3b60b7d6-13ea-4f59-a35a-1c71764f8c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583870497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.3583870497
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.2222512128
Short name T436
Test name
Test status
Simulation time 1306564887 ps
CPU time 10.14 seconds
Started Aug 09 07:16:52 PM PDT 24
Finished Aug 09 07:17:02 PM PDT 24
Peak memory 199876 kb
Host smart-357b2c03-2ea8-408e-89f1-c068ece5133c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222512128 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.2222512128
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.1717211520
Short name T412
Test name
Test status
Simulation time 31996489981 ps
CPU time 293.53 seconds
Started Aug 09 07:16:40 PM PDT 24
Finished Aug 09 07:21:34 PM PDT 24
Peak memory 601560 kb
Host smart-83b8fc6e-aef2-41c0-8907-7fef180c92a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717211520 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.1717211520
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.1801614604
Short name T96
Test name
Test status
Simulation time 37231901672 ps
CPU time 113.86 seconds
Started Aug 09 07:16:52 PM PDT 24
Finished Aug 09 07:18:46 PM PDT 24
Peak memory 199884 kb
Host smart-d6e4c228-fc8e-46c5-b169-6c3ed9164379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801614604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.1801614604
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.1314083334
Short name T450
Test name
Test status
Simulation time 20745663 ps
CPU time 0.56 seconds
Started Aug 09 07:16:48 PM PDT 24
Finished Aug 09 07:16:48 PM PDT 24
Peak memory 194772 kb
Host smart-94cf013e-71c3-400a-aeb5-c40f8665004e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314083334 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.1314083334
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.953418751
Short name T174
Test name
Test status
Simulation time 171206508 ps
CPU time 10.24 seconds
Started Aug 09 07:16:55 PM PDT 24
Finished Aug 09 07:17:05 PM PDT 24
Peak memory 199836 kb
Host smart-aa8c117f-707d-4287-a351-4ac0fcadbbcf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=953418751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.953418751
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.2111461737
Short name T16
Test name
Test status
Simulation time 12507531386 ps
CPU time 40.42 seconds
Started Aug 09 07:16:48 PM PDT 24
Finished Aug 09 07:17:29 PM PDT 24
Peak memory 199916 kb
Host smart-cc286df7-560b-4e90-994d-6f5aaf902b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111461737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.2111461737
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.2669092521
Short name T263
Test name
Test status
Simulation time 10499173947 ps
CPU time 495.48 seconds
Started Aug 09 07:16:53 PM PDT 24
Finished Aug 09 07:25:09 PM PDT 24
Peak memory 698212 kb
Host smart-e244cca6-56e0-4912-be2d-8df451367e4a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2669092521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.2669092521
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.994034191
Short name T257
Test name
Test status
Simulation time 4178423577 ps
CPU time 98.93 seconds
Started Aug 09 07:16:51 PM PDT 24
Finished Aug 09 07:18:30 PM PDT 24
Peak memory 199864 kb
Host smart-d8a79bc5-e948-461e-a228-28acd8a0dad1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994034191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.994034191
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.4180206651
Short name T418
Test name
Test status
Simulation time 2150131090 ps
CPU time 110.46 seconds
Started Aug 09 07:16:50 PM PDT 24
Finished Aug 09 07:18:41 PM PDT 24
Peak memory 199932 kb
Host smart-d178488a-4805-4c04-a756-b09c81e80f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180206651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.4180206651
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.3998424009
Short name T6
Test name
Test status
Simulation time 876272166 ps
CPU time 9.74 seconds
Started Aug 09 07:16:54 PM PDT 24
Finished Aug 09 07:17:04 PM PDT 24
Peak memory 199880 kb
Host smart-52be83f0-235e-43a3-83f0-b61e6791c206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998424009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.3998424009
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.703852220
Short name T84
Test name
Test status
Simulation time 15614995848 ps
CPU time 274.41 seconds
Started Aug 09 07:16:57 PM PDT 24
Finished Aug 09 07:21:32 PM PDT 24
Peak memory 415428 kb
Host smart-907beaf4-4f48-4c40-b29d-5547c2149fd2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703852220 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.703852220
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.167435704
Short name T481
Test name
Test status
Simulation time 3075624111 ps
CPU time 51.92 seconds
Started Aug 09 07:16:50 PM PDT 24
Finished Aug 09 07:17:42 PM PDT 24
Peak memory 199940 kb
Host smart-95dcd585-d7fd-44a7-97e0-b7a956a3ec05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167435704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.167435704
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.1025600295
Short name T225
Test name
Test status
Simulation time 20199578 ps
CPU time 0.57 seconds
Started Aug 09 07:16:50 PM PDT 24
Finished Aug 09 07:16:51 PM PDT 24
Peak memory 196632 kb
Host smart-0f0e9fa5-e5b8-41d4-a36a-ef47d47f1ad7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025600295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.1025600295
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.1353152956
Short name T42
Test name
Test status
Simulation time 1668118272 ps
CPU time 23.46 seconds
Started Aug 09 07:16:50 PM PDT 24
Finished Aug 09 07:17:14 PM PDT 24
Peak memory 199840 kb
Host smart-b09580bb-fccb-46d8-8097-0f5b28055013
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1353152956 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.1353152956
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.1310310908
Short name T458
Test name
Test status
Simulation time 1180862643 ps
CPU time 16.14 seconds
Started Aug 09 07:16:49 PM PDT 24
Finished Aug 09 07:17:06 PM PDT 24
Peak memory 199924 kb
Host smart-8100066a-9762-4f9a-bc7f-8682f39c9769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310310908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.1310310908
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.818266064
Short name T389
Test name
Test status
Simulation time 16421108487 ps
CPU time 822.19 seconds
Started Aug 09 07:16:52 PM PDT 24
Finished Aug 09 07:30:34 PM PDT 24
Peak memory 756532 kb
Host smart-5b558746-0875-4aaa-a9c7-bab19ac191d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=818266064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.818266064
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.3822107283
Short name T302
Test name
Test status
Simulation time 26603342469 ps
CPU time 270.76 seconds
Started Aug 09 07:16:54 PM PDT 24
Finished Aug 09 07:21:25 PM PDT 24
Peak memory 200108 kb
Host smart-f1b47f58-a854-4b80-815c-d826c856ca78
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822107283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.3822107283
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.934637594
Short name T150
Test name
Test status
Simulation time 31682865873 ps
CPU time 29.29 seconds
Started Aug 09 07:16:51 PM PDT 24
Finished Aug 09 07:17:20 PM PDT 24
Peak memory 199908 kb
Host smart-a079ba36-6938-44c3-bdb6-d112d032f64f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934637594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.934637594
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.2651890999
Short name T238
Test name
Test status
Simulation time 770297091 ps
CPU time 9.44 seconds
Started Aug 09 07:16:49 PM PDT 24
Finished Aug 09 07:16:58 PM PDT 24
Peak memory 199900 kb
Host smart-9eee8eb2-482e-4017-8326-0b21d3508e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651890999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.2651890999
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.1142142605
Short name T367
Test name
Test status
Simulation time 937550628844 ps
CPU time 1528.42 seconds
Started Aug 09 07:16:50 PM PDT 24
Finished Aug 09 07:42:19 PM PDT 24
Peak memory 729192 kb
Host smart-354732ed-bac7-4b27-8c59-6428851bff4d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142142605 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.1142142605
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.2663717757
Short name T456
Test name
Test status
Simulation time 646384281 ps
CPU time 9.21 seconds
Started Aug 09 07:16:50 PM PDT 24
Finished Aug 09 07:16:59 PM PDT 24
Peak memory 200100 kb
Host smart-82e49354-a27f-4a33-a682-fd93d645b997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663717757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.2663717757
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.3413574885
Short name T158
Test name
Test status
Simulation time 17148952 ps
CPU time 0.64 seconds
Started Aug 09 07:16:52 PM PDT 24
Finished Aug 09 07:16:52 PM PDT 24
Peak memory 195928 kb
Host smart-684e78a8-fa80-48cf-8b61-fb45e5068b4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413574885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.3413574885
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.2364181191
Short name T498
Test name
Test status
Simulation time 2715803549 ps
CPU time 39.71 seconds
Started Aug 09 07:17:00 PM PDT 24
Finished Aug 09 07:17:40 PM PDT 24
Peak memory 199880 kb
Host smart-0833674e-1d56-4c02-bee4-30c38de5f4a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2364181191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.2364181191
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.925770068
Short name T185
Test name
Test status
Simulation time 1339532756 ps
CPU time 18.41 seconds
Started Aug 09 07:16:56 PM PDT 24
Finished Aug 09 07:17:15 PM PDT 24
Peak memory 199796 kb
Host smart-132f7282-beef-40f8-a11b-209995eab920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925770068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.925770068
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.1483553233
Short name T265
Test name
Test status
Simulation time 9053959625 ps
CPU time 773.71 seconds
Started Aug 09 07:16:51 PM PDT 24
Finished Aug 09 07:29:45 PM PDT 24
Peak memory 688740 kb
Host smart-483e4f81-f0d3-4afb-a162-d00c0b17f1d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1483553233 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.1483553233
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.4243457312
Short name T148
Test name
Test status
Simulation time 1009640335 ps
CPU time 54.31 seconds
Started Aug 09 07:16:53 PM PDT 24
Finished Aug 09 07:17:47 PM PDT 24
Peak memory 199828 kb
Host smart-be8294b7-24cf-4a61-adb0-6ddc7f0d1eb3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243457312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.4243457312
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.4141067495
Short name T483
Test name
Test status
Simulation time 1633415793 ps
CPU time 45.5 seconds
Started Aug 09 07:16:49 PM PDT 24
Finished Aug 09 07:17:35 PM PDT 24
Peak memory 199820 kb
Host smart-ff916894-0566-4a89-b067-eb5627717c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141067495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.4141067495
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.2884891785
Short name T513
Test name
Test status
Simulation time 66710055 ps
CPU time 3.01 seconds
Started Aug 09 07:16:53 PM PDT 24
Finished Aug 09 07:16:57 PM PDT 24
Peak memory 199840 kb
Host smart-3da1d37c-b489-42de-82cd-0275141468fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884891785 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.2884891785
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.1375081885
Short name T510
Test name
Test status
Simulation time 12028219794 ps
CPU time 195.11 seconds
Started Aug 09 07:16:54 PM PDT 24
Finished Aug 09 07:20:09 PM PDT 24
Peak memory 199940 kb
Host smart-7bf2b736-6ca6-4b91-a8b6-201faec85100
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375081885 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.1375081885
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.218207084
Short name T212
Test name
Test status
Simulation time 1277063772 ps
CPU time 49.56 seconds
Started Aug 09 07:16:54 PM PDT 24
Finished Aug 09 07:17:43 PM PDT 24
Peak memory 199828 kb
Host smart-37a22843-429a-427a-855f-d037eb52e8cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218207084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.218207084
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.2860835894
Short name T400
Test name
Test status
Simulation time 12459738 ps
CPU time 0.6 seconds
Started Aug 09 07:16:11 PM PDT 24
Finished Aug 09 07:16:12 PM PDT 24
Peak memory 195944 kb
Host smart-0300f8a9-298f-414e-93af-97f44eadfc20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860835894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.2860835894
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.2115590702
Short name T205
Test name
Test status
Simulation time 6400604047 ps
CPU time 49.99 seconds
Started Aug 09 07:16:04 PM PDT 24
Finished Aug 09 07:16:54 PM PDT 24
Peak memory 199888 kb
Host smart-049f77d0-a744-489a-bbee-11ff367eeeb3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2115590702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.2115590702
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.1187981502
Short name T17
Test name
Test status
Simulation time 782185844 ps
CPU time 36.35 seconds
Started Aug 09 07:16:02 PM PDT 24
Finished Aug 09 07:16:38 PM PDT 24
Peak memory 199816 kb
Host smart-602a9f7c-7aaa-4396-abe1-88cc9fcd3535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187981502 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.1187981502
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.2045549343
Short name T360
Test name
Test status
Simulation time 4964966873 ps
CPU time 987.5 seconds
Started Aug 09 07:16:06 PM PDT 24
Finished Aug 09 07:32:34 PM PDT 24
Peak memory 728692 kb
Host smart-897925a1-a67f-497c-8414-f19ac749732b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2045549343 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.2045549343
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.424473246
Short name T517
Test name
Test status
Simulation time 12424030830 ps
CPU time 203.09 seconds
Started Aug 09 07:16:03 PM PDT 24
Finished Aug 09 07:19:27 PM PDT 24
Peak memory 198440 kb
Host smart-5372ef55-569d-4ee5-8120-5501cdc1361a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424473246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.424473246
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.344730566
Short name T368
Test name
Test status
Simulation time 3688336768 ps
CPU time 108.9 seconds
Started Aug 09 07:16:06 PM PDT 24
Finished Aug 09 07:17:55 PM PDT 24
Peak memory 199948 kb
Host smart-ff4e01ff-040d-4a44-8e51-8f74b88a886d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344730566 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.344730566
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.2457945833
Short name T56
Test name
Test status
Simulation time 153162797 ps
CPU time 1 seconds
Started Aug 09 07:16:00 PM PDT 24
Finished Aug 09 07:16:01 PM PDT 24
Peak memory 219428 kb
Host smart-72d47bfc-4eea-40f6-8fe6-ba07d2f8109d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457945833 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.2457945833
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.3530303541
Short name T307
Test name
Test status
Simulation time 842186423 ps
CPU time 14.33 seconds
Started Aug 09 07:16:15 PM PDT 24
Finished Aug 09 07:16:30 PM PDT 24
Peak memory 199812 kb
Host smart-3259d5e4-98f9-45cf-97d8-74df006ed377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530303541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.3530303541
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.2051802749
Short name T352
Test name
Test status
Simulation time 24769726862 ps
CPU time 331.11 seconds
Started Aug 09 07:16:01 PM PDT 24
Finished Aug 09 07:21:32 PM PDT 24
Peak memory 199896 kb
Host smart-f1598fdb-f8c9-4b9b-ae4a-48ec272eb1cd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051802749 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.2051802749
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_test_hmac256_vectors.1948464298
Short name T213
Test name
Test status
Simulation time 1592055401 ps
CPU time 61.86 seconds
Started Aug 09 07:16:02 PM PDT 24
Finished Aug 09 07:17:04 PM PDT 24
Peak memory 198400 kb
Host smart-acaf12f6-db78-4c34-ac35-8cf0b116268f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1948464298 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac256_vectors.1948464298
Directory /workspace/3.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac384_vectors.4100834235
Short name T121
Test name
Test status
Simulation time 5061300527 ps
CPU time 68.42 seconds
Started Aug 09 07:16:05 PM PDT 24
Finished Aug 09 07:17:13 PM PDT 24
Peak memory 199940 kb
Host smart-326f8578-3151-45c0-92fb-2fd58aecb297
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4100834235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac384_vectors.4100834235
Directory /workspace/3.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac512_vectors.544652279
Short name T167
Test name
Test status
Simulation time 8611829125 ps
CPU time 71.35 seconds
Started Aug 09 07:16:01 PM PDT 24
Finished Aug 09 07:17:12 PM PDT 24
Peak memory 199888 kb
Host smart-5cbc5de8-0367-4246-a6e4-7bb9c34527a2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=544652279 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac512_vectors.544652279
Directory /workspace/3.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha256_vectors.3076081471
Short name T419
Test name
Test status
Simulation time 9363386116 ps
CPU time 504.65 seconds
Started Aug 09 07:16:01 PM PDT 24
Finished Aug 09 07:24:26 PM PDT 24
Peak memory 199876 kb
Host smart-e8e84f45-93e9-4081-8f3e-100990f5dcc9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3076081471 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha256_vectors.3076081471
Directory /workspace/3.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha384_vectors.1853099204
Short name T366
Test name
Test status
Simulation time 399549857579 ps
CPU time 2558.03 seconds
Started Aug 09 07:16:00 PM PDT 24
Finished Aug 09 07:58:43 PM PDT 24
Peak memory 215456 kb
Host smart-38c19901-8efb-46ae-80d3-044d0028cac2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1853099204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha384_vectors.1853099204
Directory /workspace/3.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha512_vectors.2719411021
Short name T354
Test name
Test status
Simulation time 35410544663 ps
CPU time 2042.65 seconds
Started Aug 09 07:16:00 PM PDT 24
Finished Aug 09 07:50:03 PM PDT 24
Peak memory 215632 kb
Host smart-8bbc3181-f112-4c73-8ef1-de2b37b0702e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2719411021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha512_vectors.2719411021
Directory /workspace/3.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.818498426
Short name T466
Test name
Test status
Simulation time 4620460609 ps
CPU time 53.66 seconds
Started Aug 09 07:16:19 PM PDT 24
Finished Aug 09 07:17:13 PM PDT 24
Peak memory 199928 kb
Host smart-e8e91676-5583-4c6f-a49c-b49d4732b7bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818498426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.818498426
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.986359761
Short name T454
Test name
Test status
Simulation time 44146098 ps
CPU time 0.56 seconds
Started Aug 09 07:16:54 PM PDT 24
Finished Aug 09 07:16:55 PM PDT 24
Peak memory 195592 kb
Host smart-edbf4b36-4928-4b9f-ba30-aa9c709c6d65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986359761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.986359761
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.946852923
Short name T312
Test name
Test status
Simulation time 339903424 ps
CPU time 18.66 seconds
Started Aug 09 07:16:59 PM PDT 24
Finished Aug 09 07:17:18 PM PDT 24
Peak memory 199820 kb
Host smart-d5a88ae1-08c1-40d8-9eba-b90dfa89700d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946852923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.946852923
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.4221619293
Short name T478
Test name
Test status
Simulation time 35060426496 ps
CPU time 1268 seconds
Started Aug 09 07:16:54 PM PDT 24
Finished Aug 09 07:38:02 PM PDT 24
Peak memory 731620 kb
Host smart-cf7ba1c1-00eb-4bda-ab36-6aefda9bae0d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4221619293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.4221619293
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.1169520381
Short name T234
Test name
Test status
Simulation time 3004731565 ps
CPU time 170.03 seconds
Started Aug 09 07:16:52 PM PDT 24
Finished Aug 09 07:19:43 PM PDT 24
Peak memory 199820 kb
Host smart-4890b93f-e363-4568-8942-d7933e2097e8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169520381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.1169520381
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.2256942050
Short name T241
Test name
Test status
Simulation time 553605500 ps
CPU time 32.73 seconds
Started Aug 09 07:16:54 PM PDT 24
Finished Aug 09 07:17:27 PM PDT 24
Peak memory 199812 kb
Host smart-cb939efe-00c1-40a2-aa78-e4045e2dd86b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256942050 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.2256942050
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.3042853497
Short name T502
Test name
Test status
Simulation time 1426599950 ps
CPU time 10.39 seconds
Started Aug 09 07:16:54 PM PDT 24
Finished Aug 09 07:17:04 PM PDT 24
Peak memory 199772 kb
Host smart-0ab138b3-1699-441a-a056-e302f6b59cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042853497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.3042853497
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.1976530108
Short name T83
Test name
Test status
Simulation time 396610411953 ps
CPU time 2832.69 seconds
Started Aug 09 07:16:54 PM PDT 24
Finished Aug 09 08:04:07 PM PDT 24
Peak memory 794204 kb
Host smart-db93790e-2097-420d-b911-c20a9342b0f1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976530108 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.1976530108
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.2008196723
Short name T305
Test name
Test status
Simulation time 3602861333 ps
CPU time 78.26 seconds
Started Aug 09 07:16:54 PM PDT 24
Finished Aug 09 07:18:13 PM PDT 24
Peak memory 199828 kb
Host smart-aac6f372-a252-4140-b883-370df8990973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008196723 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.2008196723
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.3301431385
Short name T180
Test name
Test status
Simulation time 31876550 ps
CPU time 0.58 seconds
Started Aug 09 07:16:54 PM PDT 24
Finished Aug 09 07:16:55 PM PDT 24
Peak memory 194848 kb
Host smart-706859ec-2599-4fa8-abac-cdebfcb1bb81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301431385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.3301431385
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.2406570145
Short name T157
Test name
Test status
Simulation time 491090620 ps
CPU time 6.92 seconds
Started Aug 09 07:16:53 PM PDT 24
Finished Aug 09 07:17:00 PM PDT 24
Peak memory 199732 kb
Host smart-d61d858d-b9c0-4c0a-b0ed-c11f750c5d65
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2406570145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.2406570145
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.2782665454
Short name T276
Test name
Test status
Simulation time 6786144703 ps
CPU time 61.46 seconds
Started Aug 09 07:17:07 PM PDT 24
Finished Aug 09 07:18:09 PM PDT 24
Peak memory 199880 kb
Host smart-b49f8708-654f-4ecf-8328-7f791aeb76c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782665454 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.2782665454
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.3655130266
Short name T503
Test name
Test status
Simulation time 3820303647 ps
CPU time 665.5 seconds
Started Aug 09 07:16:52 PM PDT 24
Finished Aug 09 07:27:58 PM PDT 24
Peak memory 661844 kb
Host smart-ff899a49-d947-4cb6-aef9-d1873b7da45e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3655130266 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.3655130266
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.2007489462
Short name T391
Test name
Test status
Simulation time 45469921787 ps
CPU time 198.35 seconds
Started Aug 09 07:16:59 PM PDT 24
Finished Aug 09 07:20:17 PM PDT 24
Peak memory 199908 kb
Host smart-f5b09910-5a3f-44a4-b2c2-3e95614e6ed8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007489462 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.2007489462
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.3287446519
Short name T331
Test name
Test status
Simulation time 5508278976 ps
CPU time 99.43 seconds
Started Aug 09 07:16:53 PM PDT 24
Finished Aug 09 07:18:33 PM PDT 24
Peak memory 199884 kb
Host smart-7c213e6d-5760-4794-834e-194cf4ba1867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287446519 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.3287446519
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.2389130340
Short name T1
Test name
Test status
Simulation time 2322729454 ps
CPU time 8.63 seconds
Started Aug 09 07:16:54 PM PDT 24
Finished Aug 09 07:17:02 PM PDT 24
Peak memory 199912 kb
Host smart-1c0d16ec-4342-4043-bf57-258b402150e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389130340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.2389130340
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.1645560680
Short name T525
Test name
Test status
Simulation time 23473882203 ps
CPU time 316.01 seconds
Started Aug 09 07:16:55 PM PDT 24
Finished Aug 09 07:22:11 PM PDT 24
Peak memory 633556 kb
Host smart-a5ca67b1-1f77-4761-98fa-31ad0221fc05
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645560680 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.1645560680
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.1080154619
Short name T350
Test name
Test status
Simulation time 30624904505 ps
CPU time 60.73 seconds
Started Aug 09 07:16:54 PM PDT 24
Finished Aug 09 07:17:55 PM PDT 24
Peak memory 199836 kb
Host smart-71b9a4fb-a4ff-406c-a1eb-b8e67eaf5a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080154619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.1080154619
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.3115148850
Short name T489
Test name
Test status
Simulation time 11915875 ps
CPU time 0.57 seconds
Started Aug 09 07:16:48 PM PDT 24
Finished Aug 09 07:16:49 PM PDT 24
Peak memory 195484 kb
Host smart-b8293eec-0635-4ea6-97fe-b6fa8008a770
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115148850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.3115148850
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.2662523838
Short name T373
Test name
Test status
Simulation time 463217638 ps
CPU time 15.49 seconds
Started Aug 09 07:16:54 PM PDT 24
Finished Aug 09 07:17:09 PM PDT 24
Peak memory 199824 kb
Host smart-fe682b79-79e9-4f1f-90af-b62ebb46e1a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2662523838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.2662523838
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.1266178827
Short name T223
Test name
Test status
Simulation time 3554425768 ps
CPU time 25.55 seconds
Started Aug 09 07:16:47 PM PDT 24
Finished Aug 09 07:17:12 PM PDT 24
Peak memory 199908 kb
Host smart-bd7ee0c7-506c-4164-8c96-73a5d49f94b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266178827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.1266178827
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.676637334
Short name T301
Test name
Test status
Simulation time 121608398 ps
CPU time 9.51 seconds
Started Aug 09 07:16:57 PM PDT 24
Finished Aug 09 07:17:07 PM PDT 24
Peak memory 199828 kb
Host smart-78bbbd1a-105d-4775-ae9b-0ce950a016b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=676637334 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.676637334
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.145226509
Short name T316
Test name
Test status
Simulation time 36913355846 ps
CPU time 166.17 seconds
Started Aug 09 07:16:52 PM PDT 24
Finished Aug 09 07:19:39 PM PDT 24
Peak memory 199896 kb
Host smart-8ee0d292-f991-4fef-884e-530ffcf56c86
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145226509 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.145226509
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.3746516572
Short name T424
Test name
Test status
Simulation time 2565785064 ps
CPU time 29.49 seconds
Started Aug 09 07:16:53 PM PDT 24
Finished Aug 09 07:17:22 PM PDT 24
Peak memory 199960 kb
Host smart-d14200a9-6db1-4c25-a71e-5947cf78c764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746516572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.3746516572
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.13046283
Short name T282
Test name
Test status
Simulation time 4333773428 ps
CPU time 10.82 seconds
Started Aug 09 07:16:56 PM PDT 24
Finished Aug 09 07:17:07 PM PDT 24
Peak memory 199876 kb
Host smart-cb86090e-667e-4adf-936b-f452a3447229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13046283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.13046283
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.1503792497
Short name T308
Test name
Test status
Simulation time 1104610041 ps
CPU time 55.72 seconds
Started Aug 09 07:16:48 PM PDT 24
Finished Aug 09 07:17:44 PM PDT 24
Peak memory 199812 kb
Host smart-917bce4a-8264-4e1c-8e84-877b035f9ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503792497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.1503792497
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.970065189
Short name T287
Test name
Test status
Simulation time 49905418 ps
CPU time 0.62 seconds
Started Aug 09 07:16:54 PM PDT 24
Finished Aug 09 07:16:54 PM PDT 24
Peak memory 195960 kb
Host smart-3d1a6cfe-f005-40b0-8a35-aac738ad372b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970065189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.970065189
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.438173884
Short name T370
Test name
Test status
Simulation time 4104536474 ps
CPU time 58.11 seconds
Started Aug 09 07:16:54 PM PDT 24
Finished Aug 09 07:17:52 PM PDT 24
Peak memory 200136 kb
Host smart-ce23ce90-726a-45bc-af64-28eaab050085
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=438173884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.438173884
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.4251798324
Short name T173
Test name
Test status
Simulation time 9889194970 ps
CPU time 34.67 seconds
Started Aug 09 07:16:51 PM PDT 24
Finished Aug 09 07:17:26 PM PDT 24
Peak memory 199916 kb
Host smart-b1e0d177-e402-4dc5-8d39-4dc1ddbd6f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251798324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.4251798324
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.4248708303
Short name T486
Test name
Test status
Simulation time 37318365719 ps
CPU time 514.87 seconds
Started Aug 09 07:16:52 PM PDT 24
Finished Aug 09 07:25:28 PM PDT 24
Peak memory 699616 kb
Host smart-4ea2fb9e-a387-4757-a572-2acf47a743bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4248708303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.4248708303
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.3724745
Short name T23
Test name
Test status
Simulation time 13948418630 ps
CPU time 178.81 seconds
Started Aug 09 07:16:49 PM PDT 24
Finished Aug 09 07:19:48 PM PDT 24
Peak memory 199896 kb
Host smart-6a6a38e3-e086-4bf7-8f76-c26c9f211b88
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.3724745
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.4231914322
Short name T346
Test name
Test status
Simulation time 5158573675 ps
CPU time 47.24 seconds
Started Aug 09 07:16:52 PM PDT 24
Finished Aug 09 07:17:39 PM PDT 24
Peak memory 199900 kb
Host smart-ff736a40-5dc7-4563-8a0e-545207a21473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231914322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.4231914322
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.635957686
Short name T358
Test name
Test status
Simulation time 2730298374 ps
CPU time 11.78 seconds
Started Aug 09 07:16:46 PM PDT 24
Finished Aug 09 07:16:58 PM PDT 24
Peak memory 199900 kb
Host smart-3a4a3f10-b48a-4456-8181-b11fdf4f8801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635957686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.635957686
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.1599539327
Short name T327
Test name
Test status
Simulation time 45256916811 ps
CPU time 1680.96 seconds
Started Aug 09 07:16:48 PM PDT 24
Finished Aug 09 07:44:49 PM PDT 24
Peak memory 759200 kb
Host smart-74688377-b66b-498e-8c3a-796793be631d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599539327 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.1599539327
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.318457677
Short name T26
Test name
Test status
Simulation time 1831806507 ps
CPU time 35.9 seconds
Started Aug 09 07:16:49 PM PDT 24
Finished Aug 09 07:17:25 PM PDT 24
Peak memory 199836 kb
Host smart-832a33cb-96b4-4de6-821c-b151cacc4c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318457677 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.318457677
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.651368323
Short name T61
Test name
Test status
Simulation time 16474671 ps
CPU time 0.58 seconds
Started Aug 09 07:16:50 PM PDT 24
Finished Aug 09 07:16:51 PM PDT 24
Peak memory 196620 kb
Host smart-f5cd8151-a183-4f77-86ee-eb0fb25bad97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651368323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.651368323
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.3686370074
Short name T390
Test name
Test status
Simulation time 4117273725 ps
CPU time 59.25 seconds
Started Aug 09 07:16:48 PM PDT 24
Finished Aug 09 07:17:47 PM PDT 24
Peak memory 199924 kb
Host smart-d2e1bd14-0b8b-414b-8918-ffbc787200c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3686370074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.3686370074
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.3511731745
Short name T253
Test name
Test status
Simulation time 6186771466 ps
CPU time 41.52 seconds
Started Aug 09 07:16:52 PM PDT 24
Finished Aug 09 07:17:34 PM PDT 24
Peak memory 208172 kb
Host smart-d64eb56e-5230-4b00-9cf5-f0cf72007e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511731745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.3511731745
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.826128468
Short name T184
Test name
Test status
Simulation time 5881203003 ps
CPU time 305.95 seconds
Started Aug 09 07:16:54 PM PDT 24
Finished Aug 09 07:22:00 PM PDT 24
Peak memory 635024 kb
Host smart-52e1885f-b874-44ba-9e43-f716e31d827d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=826128468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.826128468
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.3157347447
Short name T447
Test name
Test status
Simulation time 1166577408 ps
CPU time 20.08 seconds
Started Aug 09 07:16:48 PM PDT 24
Finished Aug 09 07:17:08 PM PDT 24
Peak memory 199684 kb
Host smart-7547c614-c12f-4bd4-bd5d-f5a317d10a2f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157347447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.3157347447
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.1207384368
Short name T409
Test name
Test status
Simulation time 3104977267 ps
CPU time 186.01 seconds
Started Aug 09 07:16:50 PM PDT 24
Finished Aug 09 07:19:56 PM PDT 24
Peak memory 200104 kb
Host smart-053f5728-8a77-4ac3-8e4a-3c86b26d9436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207384368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.1207384368
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.2126469226
Short name T69
Test name
Test status
Simulation time 2532663151 ps
CPU time 9.19 seconds
Started Aug 09 07:16:49 PM PDT 24
Finished Aug 09 07:16:59 PM PDT 24
Peak memory 199924 kb
Host smart-2e57c823-8159-47ec-93da-d9e5a44c5ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126469226 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.2126469226
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.3386569130
Short name T297
Test name
Test status
Simulation time 5300214120 ps
CPU time 93.91 seconds
Started Aug 09 07:16:53 PM PDT 24
Finished Aug 09 07:18:27 PM PDT 24
Peak memory 199996 kb
Host smart-e0b5ee86-3e0a-4957-b133-c242ab60fbe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386569130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.3386569130
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.4113423590
Short name T446
Test name
Test status
Simulation time 33687843 ps
CPU time 0.58 seconds
Started Aug 09 07:17:03 PM PDT 24
Finished Aug 09 07:17:04 PM PDT 24
Peak memory 195912 kb
Host smart-059487ff-2346-467b-87e0-6e69df007b03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113423590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.4113423590
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.1445819213
Short name T353
Test name
Test status
Simulation time 1048101140 ps
CPU time 14.71 seconds
Started Aug 09 07:17:00 PM PDT 24
Finished Aug 09 07:17:15 PM PDT 24
Peak memory 199764 kb
Host smart-7a6d39dc-6074-4dd8-80da-4505d626eacb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445819213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.1445819213
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.3619255343
Short name T306
Test name
Test status
Simulation time 3108550836 ps
CPU time 581.29 seconds
Started Aug 09 07:17:05 PM PDT 24
Finished Aug 09 07:26:46 PM PDT 24
Peak memory 700540 kb
Host smart-aa1bc57d-ea8a-4047-9928-a2213b803060
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3619255343 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.3619255343
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.721674093
Short name T206
Test name
Test status
Simulation time 1216934481 ps
CPU time 73.57 seconds
Started Aug 09 07:17:00 PM PDT 24
Finished Aug 09 07:18:13 PM PDT 24
Peak memory 199708 kb
Host smart-67d32a43-588d-45c0-a242-8dedab360a2f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721674093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.721674093
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.1260989955
Short name T196
Test name
Test status
Simulation time 38768171285 ps
CPU time 109.71 seconds
Started Aug 09 07:16:53 PM PDT 24
Finished Aug 09 07:18:43 PM PDT 24
Peak memory 200148 kb
Host smart-70e4ecff-d341-4701-b3b2-7acbea6b844b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260989955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.1260989955
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.2731038810
Short name T63
Test name
Test status
Simulation time 3414178098 ps
CPU time 14.67 seconds
Started Aug 09 07:16:58 PM PDT 24
Finished Aug 09 07:17:13 PM PDT 24
Peak memory 199908 kb
Host smart-797298b6-9bec-453b-9727-e1511b6b8979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731038810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.2731038810
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.1163568473
Short name T5
Test name
Test status
Simulation time 43085308387 ps
CPU time 1626.79 seconds
Started Aug 09 07:16:55 PM PDT 24
Finished Aug 09 07:44:02 PM PDT 24
Peak memory 730324 kb
Host smart-799c0113-8458-4cf0-b980-c8787a7bc57e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163568473 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.1163568473
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.234884265
Short name T464
Test name
Test status
Simulation time 15973016271 ps
CPU time 107.73 seconds
Started Aug 09 07:17:05 PM PDT 24
Finished Aug 09 07:18:53 PM PDT 24
Peak memory 199888 kb
Host smart-08991555-69ed-4642-8c0d-dc7567d13f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234884265 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.234884265
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.3620246380
Short name T451
Test name
Test status
Simulation time 56778030 ps
CPU time 0.59 seconds
Started Aug 09 07:17:05 PM PDT 24
Finished Aug 09 07:17:06 PM PDT 24
Peak memory 195940 kb
Host smart-db81df70-f67d-481d-ab52-0ddebce9eec1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620246380 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.3620246380
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.3046949590
Short name T177
Test name
Test status
Simulation time 2051690306 ps
CPU time 28.88 seconds
Started Aug 09 07:16:56 PM PDT 24
Finished Aug 09 07:17:25 PM PDT 24
Peak memory 199820 kb
Host smart-3a124128-cccb-4713-b9ae-f7cb8d160404
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3046949590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.3046949590
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.3595229223
Short name T376
Test name
Test status
Simulation time 1816991182 ps
CPU time 33.81 seconds
Started Aug 09 07:17:05 PM PDT 24
Finished Aug 09 07:17:39 PM PDT 24
Peak memory 199884 kb
Host smart-848b1222-23b8-4559-9fb0-38a5f3b2409a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595229223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.3595229223
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.879171048
Short name T40
Test name
Test status
Simulation time 1796365746 ps
CPU time 299.84 seconds
Started Aug 09 07:16:59 PM PDT 24
Finished Aug 09 07:21:59 PM PDT 24
Peak memory 621736 kb
Host smart-bf1914d7-1cbc-4e6a-9524-88ec16e807ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=879171048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.879171048
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.1357319049
Short name T494
Test name
Test status
Simulation time 70111261234 ps
CPU time 74.5 seconds
Started Aug 09 07:17:04 PM PDT 24
Finished Aug 09 07:18:19 PM PDT 24
Peak memory 199896 kb
Host smart-50381068-1875-4abd-82a9-f40735b19ef4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357319049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.1357319049
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.4060053562
Short name T36
Test name
Test status
Simulation time 853877430 ps
CPU time 50.09 seconds
Started Aug 09 07:16:55 PM PDT 24
Finished Aug 09 07:17:45 PM PDT 24
Peak memory 199904 kb
Host smart-e22b836f-5136-47df-b963-94c50a961f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060053562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.4060053562
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.1637023946
Short name T135
Test name
Test status
Simulation time 606270300 ps
CPU time 6.41 seconds
Started Aug 09 07:16:55 PM PDT 24
Finished Aug 09 07:17:01 PM PDT 24
Peak memory 199812 kb
Host smart-3c2dfd2e-4acd-49ae-84ec-825908a4ec24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637023946 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.1637023946
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.2614705006
Short name T98
Test name
Test status
Simulation time 58804195726 ps
CPU time 368.64 seconds
Started Aug 09 07:16:56 PM PDT 24
Finished Aug 09 07:23:05 PM PDT 24
Peak memory 199968 kb
Host smart-99ddfd77-da5c-4a3a-9d74-50dd1010dcfb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614705006 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.2614705006
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.3582729716
Short name T249
Test name
Test status
Simulation time 13362197907 ps
CPU time 159.87 seconds
Started Aug 09 07:17:00 PM PDT 24
Finished Aug 09 07:19:40 PM PDT 24
Peak memory 199948 kb
Host smart-ede5063a-d0c4-40cf-be7d-1b50853e42aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582729716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.3582729716
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.3039241175
Short name T58
Test name
Test status
Simulation time 13314598 ps
CPU time 0.61 seconds
Started Aug 09 07:17:06 PM PDT 24
Finished Aug 09 07:17:06 PM PDT 24
Peak memory 196652 kb
Host smart-5fac11c0-f764-4810-a5eb-bad02eba42c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039241175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.3039241175
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.2291501173
Short name T326
Test name
Test status
Simulation time 82652826 ps
CPU time 1.72 seconds
Started Aug 09 07:17:02 PM PDT 24
Finished Aug 09 07:17:04 PM PDT 24
Peak memory 199744 kb
Host smart-29342003-d786-4bd1-9c41-d5e4aed1c476
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2291501173 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.2291501173
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.477169820
Short name T314
Test name
Test status
Simulation time 5859012866 ps
CPU time 24.84 seconds
Started Aug 09 07:17:05 PM PDT 24
Finished Aug 09 07:17:30 PM PDT 24
Peak memory 199980 kb
Host smart-91e5f5da-c001-44af-9c43-277087ec8953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477169820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.477169820
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.1056231720
Short name T293
Test name
Test status
Simulation time 58261106232 ps
CPU time 1699.03 seconds
Started Aug 09 07:17:08 PM PDT 24
Finished Aug 09 07:45:27 PM PDT 24
Peak memory 785716 kb
Host smart-46c404ff-f3fb-4dae-83f7-ed17dda3e183
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1056231720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.1056231720
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.1250456796
Short name T453
Test name
Test status
Simulation time 91882817261 ps
CPU time 155.21 seconds
Started Aug 09 07:17:05 PM PDT 24
Finished Aug 09 07:19:40 PM PDT 24
Peak memory 199896 kb
Host smart-56305e8a-c2ac-4ae7-8b02-5b272cfac6c5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250456796 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.1250456796
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.2555721708
Short name T311
Test name
Test status
Simulation time 23656316476 ps
CPU time 161.82 seconds
Started Aug 09 07:17:00 PM PDT 24
Finished Aug 09 07:19:42 PM PDT 24
Peak memory 199892 kb
Host smart-1e22d25c-b497-4dcf-8f15-b38ed9b2f7c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555721708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.2555721708
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.2543760599
Short name T64
Test name
Test status
Simulation time 117782774 ps
CPU time 5.93 seconds
Started Aug 09 07:17:05 PM PDT 24
Finished Aug 09 07:17:11 PM PDT 24
Peak memory 199792 kb
Host smart-dd9cc372-cd89-4b34-aeae-19ad3769a740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543760599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.2543760599
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.177974321
Short name T62
Test name
Test status
Simulation time 78757954391 ps
CPU time 2091.21 seconds
Started Aug 09 07:17:10 PM PDT 24
Finished Aug 09 07:52:01 PM PDT 24
Peak memory 732108 kb
Host smart-526bb4ee-28b6-4f87-9b27-e4fd58ba28ee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177974321 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.177974321
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.1819745717
Short name T343
Test name
Test status
Simulation time 522001482 ps
CPU time 10.39 seconds
Started Aug 09 07:17:03 PM PDT 24
Finished Aug 09 07:17:13 PM PDT 24
Peak memory 199804 kb
Host smart-e551ac9e-ebd3-4be4-9a06-e1e654b4d646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819745717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.1819745717
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.97995361
Short name T461
Test name
Test status
Simulation time 22724281 ps
CPU time 0.57 seconds
Started Aug 09 07:17:05 PM PDT 24
Finished Aug 09 07:17:06 PM PDT 24
Peak memory 195692 kb
Host smart-d0b8edd6-afc2-4040-a7bb-4ae58bd33dad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97995361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.97995361
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.704085213
Short name T231
Test name
Test status
Simulation time 551806611 ps
CPU time 22.45 seconds
Started Aug 09 07:17:10 PM PDT 24
Finished Aug 09 07:17:33 PM PDT 24
Peak memory 199864 kb
Host smart-b8ba8828-0b63-45de-9588-a6b53e83ac30
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=704085213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.704085213
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.915327621
Short name T404
Test name
Test status
Simulation time 4007938181 ps
CPU time 60.71 seconds
Started Aug 09 07:17:04 PM PDT 24
Finished Aug 09 07:18:05 PM PDT 24
Peak memory 199816 kb
Host smart-0dc3eb18-c8f9-4046-8916-5e445c9038ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915327621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.915327621
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.2926264838
Short name T304
Test name
Test status
Simulation time 20160644020 ps
CPU time 954.24 seconds
Started Aug 09 07:17:04 PM PDT 24
Finished Aug 09 07:32:58 PM PDT 24
Peak memory 694592 kb
Host smart-7d09c5d0-b81e-4f95-83b3-2bc3d0426fed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2926264838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.2926264838
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.3996637386
Short name T348
Test name
Test status
Simulation time 1301957330 ps
CPU time 75.95 seconds
Started Aug 09 07:17:04 PM PDT 24
Finished Aug 09 07:18:21 PM PDT 24
Peak memory 199840 kb
Host smart-18f7b626-65f6-447d-9170-de48ce64e573
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996637386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.3996637386
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.4277263467
Short name T372
Test name
Test status
Simulation time 13302123545 ps
CPU time 171.16 seconds
Started Aug 09 07:17:05 PM PDT 24
Finished Aug 09 07:19:56 PM PDT 24
Peak memory 199896 kb
Host smart-61da9f72-d71e-40f7-965a-ee54ff61ca6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277263467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.4277263467
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.1312289188
Short name T50
Test name
Test status
Simulation time 1105874697 ps
CPU time 7.63 seconds
Started Aug 09 07:17:05 PM PDT 24
Finished Aug 09 07:17:12 PM PDT 24
Peak memory 199812 kb
Host smart-b938549e-efb6-40e4-b288-49bcf8a00761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312289188 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.1312289188
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.3185491065
Short name T220
Test name
Test status
Simulation time 87284998462 ps
CPU time 2260.72 seconds
Started Aug 09 07:17:04 PM PDT 24
Finished Aug 09 07:54:45 PM PDT 24
Peak memory 764468 kb
Host smart-b95100c3-3122-4fe0-8f74-c5fb8b7671ce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185491065 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.3185491065
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.4245625698
Short name T472
Test name
Test status
Simulation time 2539130733 ps
CPU time 35.18 seconds
Started Aug 09 07:17:04 PM PDT 24
Finished Aug 09 07:17:39 PM PDT 24
Peak memory 199856 kb
Host smart-2d4cd661-f823-4d8e-ac1b-ebc14834a76f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245625698 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.4245625698
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.473629589
Short name T182
Test name
Test status
Simulation time 42853121 ps
CPU time 0.56 seconds
Started Aug 09 07:17:18 PM PDT 24
Finished Aug 09 07:17:18 PM PDT 24
Peak memory 194860 kb
Host smart-72b54b86-093c-4889-95b1-401d69c9be20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473629589 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.473629589
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.1152755103
Short name T18
Test name
Test status
Simulation time 407842477 ps
CPU time 24.19 seconds
Started Aug 09 07:17:04 PM PDT 24
Finished Aug 09 07:17:29 PM PDT 24
Peak memory 199912 kb
Host smart-9eb0af0d-33dc-4819-85da-de8f6046a7c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1152755103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.1152755103
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.353058442
Short name T140
Test name
Test status
Simulation time 2892591228 ps
CPU time 14.52 seconds
Started Aug 09 07:17:10 PM PDT 24
Finished Aug 09 07:17:25 PM PDT 24
Peak memory 199868 kb
Host smart-a62c4182-3c03-4065-86b4-dfaf590185e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353058442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.353058442
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.1441309456
Short name T200
Test name
Test status
Simulation time 10640659603 ps
CPU time 422.64 seconds
Started Aug 09 07:17:09 PM PDT 24
Finished Aug 09 07:24:12 PM PDT 24
Peak memory 616568 kb
Host smart-c4a15980-5023-43ab-83db-09173df58298
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1441309456 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.1441309456
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.2003805400
Short name T262
Test name
Test status
Simulation time 1465721921 ps
CPU time 76.49 seconds
Started Aug 09 07:17:12 PM PDT 24
Finished Aug 09 07:18:29 PM PDT 24
Peak memory 199908 kb
Host smart-8c8d3ec8-18e3-4d06-9769-fd6b3e383551
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003805400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.2003805400
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.490563773
Short name T417
Test name
Test status
Simulation time 9456840465 ps
CPU time 115.75 seconds
Started Aug 09 07:17:10 PM PDT 24
Finished Aug 09 07:19:06 PM PDT 24
Peak memory 208156 kb
Host smart-2102a93a-07b3-4dd7-b439-53c37e202dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490563773 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.490563773
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.3114158565
Short name T339
Test name
Test status
Simulation time 187155719 ps
CPU time 1.32 seconds
Started Aug 09 07:17:03 PM PDT 24
Finished Aug 09 07:17:05 PM PDT 24
Peak memory 199748 kb
Host smart-cfb5d067-2229-4cc8-b356-3bea84165ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114158565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.3114158565
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.2638863906
Short name T278
Test name
Test status
Simulation time 24569323503 ps
CPU time 428.91 seconds
Started Aug 09 07:17:12 PM PDT 24
Finished Aug 09 07:24:21 PM PDT 24
Peak memory 255388 kb
Host smart-899cb7b5-b5a5-47ac-bad9-14d338c5e466
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638863906 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.2638863906
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.4266420800
Short name T187
Test name
Test status
Simulation time 1160247759 ps
CPU time 15.96 seconds
Started Aug 09 07:17:11 PM PDT 24
Finished Aug 09 07:17:27 PM PDT 24
Peak memory 199768 kb
Host smart-5a00214b-bab7-4eea-ae45-72fb1543ab89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266420800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.4266420800
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.3492555250
Short name T491
Test name
Test status
Simulation time 27589384 ps
CPU time 0.59 seconds
Started Aug 09 07:16:08 PM PDT 24
Finished Aug 09 07:16:09 PM PDT 24
Peak memory 195724 kb
Host smart-e4dcbc69-68d3-478f-a982-9bf28552be75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492555250 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.3492555250
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.2006877595
Short name T495
Test name
Test status
Simulation time 3816624926 ps
CPU time 54.23 seconds
Started Aug 09 07:16:21 PM PDT 24
Finished Aug 09 07:17:16 PM PDT 24
Peak memory 199944 kb
Host smart-8fa8d892-dbf9-4c54-821c-e0aa1a2f4c5c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2006877595 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.2006877595
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.3579990228
Short name T363
Test name
Test status
Simulation time 1758061758 ps
CPU time 46.07 seconds
Started Aug 09 07:16:04 PM PDT 24
Finished Aug 09 07:16:50 PM PDT 24
Peak memory 199832 kb
Host smart-8c228eaa-a36c-4335-a4bb-f719b4032759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579990228 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.3579990228
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.1093182670
Short name T496
Test name
Test status
Simulation time 5394907566 ps
CPU time 503.48 seconds
Started Aug 09 07:16:10 PM PDT 24
Finished Aug 09 07:24:34 PM PDT 24
Peak memory 732216 kb
Host smart-689d7ca0-dc4c-4945-8905-e5411acfe231
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1093182670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.1093182670
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.457089122
Short name T420
Test name
Test status
Simulation time 1594186008 ps
CPU time 20.21 seconds
Started Aug 09 07:16:06 PM PDT 24
Finished Aug 09 07:16:26 PM PDT 24
Peak memory 199848 kb
Host smart-0f03758c-c46b-4659-b5d2-7272656de3f4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457089122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.457089122
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.3904833297
Short name T317
Test name
Test status
Simulation time 3304146748 ps
CPU time 122.19 seconds
Started Aug 09 07:16:10 PM PDT 24
Finished Aug 09 07:18:12 PM PDT 24
Peak memory 199928 kb
Host smart-c8ea9279-8a8b-4efd-8a80-84ca9a9cdb7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904833297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.3904833297
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.640915734
Short name T54
Test name
Test status
Simulation time 284916379 ps
CPU time 0.94 seconds
Started Aug 09 07:16:01 PM PDT 24
Finished Aug 09 07:16:02 PM PDT 24
Peak memory 219568 kb
Host smart-19cff787-8cdc-4f5e-a423-16171a33b02e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640915734 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.640915734
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.90822131
Short name T178
Test name
Test status
Simulation time 1186507599 ps
CPU time 15.39 seconds
Started Aug 09 07:16:17 PM PDT 24
Finished Aug 09 07:16:33 PM PDT 24
Peak memory 199856 kb
Host smart-5265170c-3219-4ee4-a309-11c766be3381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90822131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.90822131
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.1837250441
Short name T48
Test name
Test status
Simulation time 132420271080 ps
CPU time 3758.15 seconds
Started Aug 09 07:16:02 PM PDT 24
Finished Aug 09 08:18:41 PM PDT 24
Peak memory 812636 kb
Host smart-0b4fa390-0b00-4876-aef8-61d7a033cc21
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837250441 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.1837250441
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_stress_all_with_rand_reset.681950973
Short name T25
Test name
Test status
Simulation time 172234921210 ps
CPU time 1009.67 seconds
Started Aug 09 07:16:01 PM PDT 24
Finished Aug 09 07:32:51 PM PDT 24
Peak memory 672308 kb
Host smart-94b72342-1c12-4df4-a238-79de8a0eb529
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=681950973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all_with_rand_reset.681950973
Directory /workspace/4.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.hmac_test_hmac256_vectors.1927101108
Short name T239
Test name
Test status
Simulation time 15872637192 ps
CPU time 66.9 seconds
Started Aug 09 07:16:03 PM PDT 24
Finished Aug 09 07:17:11 PM PDT 24
Peak memory 199892 kb
Host smart-b74d46a1-fefa-41d6-939f-cd0c7c110d56
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1927101108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac256_vectors.1927101108
Directory /workspace/4.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac384_vectors.182497951
Short name T146
Test name
Test status
Simulation time 6287844825 ps
CPU time 72.88 seconds
Started Aug 09 07:16:06 PM PDT 24
Finished Aug 09 07:17:19 PM PDT 24
Peak memory 199924 kb
Host smart-387a62cf-2c5e-4221-9046-16116741e560
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=182497951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac384_vectors.182497951
Directory /workspace/4.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac512_vectors.3981217787
Short name T381
Test name
Test status
Simulation time 17054922647 ps
CPU time 136.83 seconds
Started Aug 09 07:16:11 PM PDT 24
Finished Aug 09 07:18:28 PM PDT 24
Peak memory 199880 kb
Host smart-12167d6d-a843-42d2-91f7-faacc712e283
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3981217787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac512_vectors.3981217787
Directory /workspace/4.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha256_vectors.618658779
Short name T275
Test name
Test status
Simulation time 70424631166 ps
CPU time 588.54 seconds
Started Aug 09 07:16:02 PM PDT 24
Finished Aug 09 07:25:50 PM PDT 24
Peak memory 199872 kb
Host smart-400579fa-0ef1-476e-866d-84d2a1e37bd3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=618658779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha256_vectors.618658779
Directory /workspace/4.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha384_vectors.94267830
Short name T497
Test name
Test status
Simulation time 1148029893408 ps
CPU time 2459.62 seconds
Started Aug 09 07:16:01 PM PDT 24
Finished Aug 09 07:57:01 PM PDT 24
Peak memory 216304 kb
Host smart-9a5072ae-65a7-4288-af9a-e80640995868
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=94267830 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha384_vectors.94267830
Directory /workspace/4.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha512_vectors.4174326828
Short name T359
Test name
Test status
Simulation time 212530415970 ps
CPU time 2647.56 seconds
Started Aug 09 07:16:21 PM PDT 24
Finished Aug 09 08:00:29 PM PDT 24
Peak memory 216208 kb
Host smart-4bf19e38-9291-4c74-99da-b4ceb8fd20e9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4174326828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha512_vectors.4174326828
Directory /workspace/4.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.4226323069
Short name T221
Test name
Test status
Simulation time 7934218902 ps
CPU time 64.79 seconds
Started Aug 09 07:16:16 PM PDT 24
Finished Aug 09 07:17:21 PM PDT 24
Peak memory 199952 kb
Host smart-6275e047-4484-404c-bf2a-31b160dfafe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226323069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.4226323069
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.3315270042
Short name T259
Test name
Test status
Simulation time 12738058 ps
CPU time 0.64 seconds
Started Aug 09 07:17:11 PM PDT 24
Finished Aug 09 07:17:12 PM PDT 24
Peak memory 196640 kb
Host smart-2bbeaeb9-424d-46ae-ada5-2f29390a6123
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315270042 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.3315270042
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.232867528
Short name T523
Test name
Test status
Simulation time 963354941 ps
CPU time 28.41 seconds
Started Aug 09 07:17:11 PM PDT 24
Finished Aug 09 07:17:40 PM PDT 24
Peak memory 199912 kb
Host smart-89fe4d04-c1db-4947-a7a5-15d1f326ec1f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=232867528 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.232867528
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.1708373224
Short name T442
Test name
Test status
Simulation time 2351631475 ps
CPU time 9.09 seconds
Started Aug 09 07:17:18 PM PDT 24
Finished Aug 09 07:17:27 PM PDT 24
Peak memory 199852 kb
Host smart-5481ed73-05cf-4616-8a6b-54d1dd575af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708373224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.1708373224
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.2707646606
Short name T364
Test name
Test status
Simulation time 104740987819 ps
CPU time 1228.37 seconds
Started Aug 09 07:17:12 PM PDT 24
Finished Aug 09 07:37:40 PM PDT 24
Peak memory 795792 kb
Host smart-d1b13777-6fcd-43c8-b4ac-982bcf450844
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2707646606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.2707646606
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.1601635794
Short name T501
Test name
Test status
Simulation time 32815147 ps
CPU time 0.71 seconds
Started Aug 09 07:17:11 PM PDT 24
Finished Aug 09 07:17:12 PM PDT 24
Peak memory 196324 kb
Host smart-aa9a3021-4055-4c16-b210-f879a785ec3c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601635794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.1601635794
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.2183484352
Short name T425
Test name
Test status
Simulation time 2049363280 ps
CPU time 29.12 seconds
Started Aug 09 07:17:12 PM PDT 24
Finished Aug 09 07:17:41 PM PDT 24
Peak memory 199900 kb
Host smart-7435c587-9385-4a11-80ab-beab7a567c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183484352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.2183484352
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.2847211783
Short name T374
Test name
Test status
Simulation time 119104571 ps
CPU time 5.76 seconds
Started Aug 09 07:17:12 PM PDT 24
Finished Aug 09 07:17:18 PM PDT 24
Peak memory 199872 kb
Host smart-a532bd2d-5dab-4aba-9b69-c522e97ff80c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847211783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.2847211783
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.4221279437
Short name T81
Test name
Test status
Simulation time 475521202958 ps
CPU time 1054.42 seconds
Started Aug 09 07:17:10 PM PDT 24
Finished Aug 09 07:34:45 PM PDT 24
Peak memory 490628 kb
Host smart-d89059f6-79ad-4354-9d50-a76cb5417e14
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221279437 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.4221279437
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.3414116956
Short name T490
Test name
Test status
Simulation time 7817587915 ps
CPU time 37.75 seconds
Started Aug 09 07:17:11 PM PDT 24
Finished Aug 09 07:17:49 PM PDT 24
Peak memory 199924 kb
Host smart-b37d119b-2efc-42d6-a2c4-54b6e8344697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414116956 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.3414116956
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.2576188264
Short name T22
Test name
Test status
Simulation time 13382438 ps
CPU time 0.6 seconds
Started Aug 09 07:17:22 PM PDT 24
Finished Aug 09 07:17:22 PM PDT 24
Peak memory 195904 kb
Host smart-19cc1590-fde2-47aa-a18d-0b763f94cff7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576188264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.2576188264
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.2891428839
Short name T191
Test name
Test status
Simulation time 2075302898 ps
CPU time 62.89 seconds
Started Aug 09 07:17:11 PM PDT 24
Finished Aug 09 07:18:14 PM PDT 24
Peak memory 199808 kb
Host smart-d40b5628-e0c3-490c-b4f1-2ae6588bddf6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2891428839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.2891428839
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.633039521
Short name T511
Test name
Test status
Simulation time 2276770956 ps
CPU time 30.41 seconds
Started Aug 09 07:17:18 PM PDT 24
Finished Aug 09 07:17:48 PM PDT 24
Peak memory 199872 kb
Host smart-414b5a24-a80b-453e-be52-c5f4d632fb6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633039521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.633039521
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.2476271401
Short name T507
Test name
Test status
Simulation time 5457116113 ps
CPU time 926.31 seconds
Started Aug 09 07:17:11 PM PDT 24
Finished Aug 09 07:32:38 PM PDT 24
Peak memory 718056 kb
Host smart-ca23473f-cef9-487f-8efe-b54ba4c4d8ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2476271401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.2476271401
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.201203728
Short name T247
Test name
Test status
Simulation time 6487663629 ps
CPU time 158.84 seconds
Started Aug 09 07:17:18 PM PDT 24
Finished Aug 09 07:19:57 PM PDT 24
Peak memory 199900 kb
Host smart-668fe9dc-83ef-439e-ba5d-af5083444226
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201203728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.201203728
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.3016421852
Short name T369
Test name
Test status
Simulation time 43580979145 ps
CPU time 32.59 seconds
Started Aug 09 07:17:11 PM PDT 24
Finished Aug 09 07:17:44 PM PDT 24
Peak memory 199904 kb
Host smart-e789ebfc-009f-44bd-8507-52188af93bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016421852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.3016421852
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.206862174
Short name T431
Test name
Test status
Simulation time 335336035 ps
CPU time 3.84 seconds
Started Aug 09 07:17:11 PM PDT 24
Finished Aug 09 07:17:15 PM PDT 24
Peak memory 199812 kb
Host smart-f6c89c70-c722-4b79-af22-8cbea5701360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206862174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.206862174
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.2993365259
Short name T161
Test name
Test status
Simulation time 72939183776 ps
CPU time 2211.53 seconds
Started Aug 09 07:17:18 PM PDT 24
Finished Aug 09 07:54:10 PM PDT 24
Peak memory 759832 kb
Host smart-0f7cca31-9a07-4927-bb53-0c600330b333
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993365259 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.2993365259
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.3547988583
Short name T189
Test name
Test status
Simulation time 3002230159 ps
CPU time 26.1 seconds
Started Aug 09 07:17:18 PM PDT 24
Finished Aug 09 07:17:44 PM PDT 24
Peak memory 199908 kb
Host smart-8b51f274-e4c8-4773-9283-1d29633e8332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547988583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.3547988583
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.219906691
Short name T467
Test name
Test status
Simulation time 103575571 ps
CPU time 0.57 seconds
Started Aug 09 07:17:19 PM PDT 24
Finished Aug 09 07:17:19 PM PDT 24
Peak memory 195672 kb
Host smart-c750f64a-e5ef-42d1-8759-758680c022ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219906691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.219906691
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.4223268743
Short name T445
Test name
Test status
Simulation time 3867414562 ps
CPU time 58.32 seconds
Started Aug 09 07:17:19 PM PDT 24
Finished Aug 09 07:18:17 PM PDT 24
Peak memory 199952 kb
Host smart-5619d758-b55b-47b7-98ad-f5c28da42cb2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4223268743 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.4223268743
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.2989721426
Short name T219
Test name
Test status
Simulation time 5117287936 ps
CPU time 67.3 seconds
Started Aug 09 07:17:18 PM PDT 24
Finished Aug 09 07:18:25 PM PDT 24
Peak memory 208100 kb
Host smart-7c254d6d-b08e-421b-ac3e-6ca3a3ee3043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989721426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.2989721426
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.325920686
Short name T318
Test name
Test status
Simulation time 5370190700 ps
CPU time 412.7 seconds
Started Aug 09 07:17:21 PM PDT 24
Finished Aug 09 07:24:14 PM PDT 24
Peak memory 666344 kb
Host smart-f70ccf15-31dc-419f-b15d-d8234e740b82
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=325920686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.325920686
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.3821540311
Short name T77
Test name
Test status
Simulation time 5953777314 ps
CPU time 70.91 seconds
Started Aug 09 07:17:22 PM PDT 24
Finished Aug 09 07:18:33 PM PDT 24
Peak memory 199884 kb
Host smart-f76506d2-cc62-41cb-9587-d0d087a9661f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821540311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.3821540311
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.2008850426
Short name T190
Test name
Test status
Simulation time 25284333702 ps
CPU time 69.07 seconds
Started Aug 09 07:17:22 PM PDT 24
Finished Aug 09 07:18:31 PM PDT 24
Peak memory 199900 kb
Host smart-f6b5a858-ec19-4a14-a887-aaa5c8427c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008850426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.2008850426
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.4109540051
Short name T159
Test name
Test status
Simulation time 271618411 ps
CPU time 11.96 seconds
Started Aug 09 07:17:19 PM PDT 24
Finished Aug 09 07:17:31 PM PDT 24
Peak memory 199824 kb
Host smart-c0d98e03-3502-4874-9a0d-bdcabc49b22c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109540051 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.4109540051
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.290877985
Short name T218
Test name
Test status
Simulation time 36250147219 ps
CPU time 1675.32 seconds
Started Aug 09 07:17:17 PM PDT 24
Finished Aug 09 07:45:13 PM PDT 24
Peak memory 805772 kb
Host smart-13323941-77a9-482d-be79-2e2e1a357431
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290877985 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.290877985
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.3307128889
Short name T233
Test name
Test status
Simulation time 3119220983 ps
CPU time 59.03 seconds
Started Aug 09 07:17:18 PM PDT 24
Finished Aug 09 07:18:17 PM PDT 24
Peak memory 199828 kb
Host smart-5c80875b-577b-4784-a93e-db8a72fd6455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307128889 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.3307128889
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.2225716761
Short name T480
Test name
Test status
Simulation time 59403605 ps
CPU time 0.59 seconds
Started Aug 09 07:17:18 PM PDT 24
Finished Aug 09 07:17:19 PM PDT 24
Peak memory 195856 kb
Host smart-a2474201-8dbe-4f7c-8bcc-a7e33ac3cffd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225716761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.2225716761
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.2868972589
Short name T434
Test name
Test status
Simulation time 269747297 ps
CPU time 16.39 seconds
Started Aug 09 07:17:18 PM PDT 24
Finished Aug 09 07:17:34 PM PDT 24
Peak memory 199900 kb
Host smart-fd0e6828-c902-461f-9b2f-d4899babb6fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2868972589 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.2868972589
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.4157003507
Short name T267
Test name
Test status
Simulation time 4160289324 ps
CPU time 52.85 seconds
Started Aug 09 07:17:21 PM PDT 24
Finished Aug 09 07:18:14 PM PDT 24
Peak memory 199892 kb
Host smart-49a43e03-64b0-404d-acd9-09f03a3b3d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157003507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.4157003507
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.4228572537
Short name T139
Test name
Test status
Simulation time 35817386115 ps
CPU time 1756.56 seconds
Started Aug 09 07:17:20 PM PDT 24
Finished Aug 09 07:46:37 PM PDT 24
Peak memory 789280 kb
Host smart-3fcbbfce-9a20-47e3-9775-315c83a66b27
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4228572537 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.4228572537
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.1903219181
Short name T151
Test name
Test status
Simulation time 3683105168 ps
CPU time 186.35 seconds
Started Aug 09 07:17:20 PM PDT 24
Finished Aug 09 07:20:27 PM PDT 24
Peak memory 199944 kb
Host smart-22f98eb2-b4cb-4dbc-af2c-8b47af0c9b25
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903219181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.1903219181
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.695600244
Short name T351
Test name
Test status
Simulation time 367656999 ps
CPU time 20.13 seconds
Started Aug 09 07:17:18 PM PDT 24
Finished Aug 09 07:17:39 PM PDT 24
Peak memory 199872 kb
Host smart-d50b84fc-2c9f-4c7c-9997-ee7ce3042a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695600244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.695600244
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.1681806035
Short name T89
Test name
Test status
Simulation time 1109822687 ps
CPU time 9.37 seconds
Started Aug 09 07:17:18 PM PDT 24
Finished Aug 09 07:17:27 PM PDT 24
Peak memory 199828 kb
Host smart-76387eb5-9e7d-461b-9666-1461c169069e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681806035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.1681806035
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.4090153764
Short name T141
Test name
Test status
Simulation time 11827081942 ps
CPU time 154.23 seconds
Started Aug 09 07:17:17 PM PDT 24
Finished Aug 09 07:19:52 PM PDT 24
Peak memory 199924 kb
Host smart-6578a915-0f18-419f-b676-1e301431d07d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090153764 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.4090153764
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.3506525980
Short name T422
Test name
Test status
Simulation time 18559870418 ps
CPU time 85.77 seconds
Started Aug 09 07:17:18 PM PDT 24
Finished Aug 09 07:18:44 PM PDT 24
Peak memory 199872 kb
Host smart-2d7b8bae-c748-407e-bb3f-3401bd90abfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506525980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.3506525980
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.1442347640
Short name T332
Test name
Test status
Simulation time 11164212 ps
CPU time 0.58 seconds
Started Aug 09 07:17:29 PM PDT 24
Finished Aug 09 07:17:29 PM PDT 24
Peak memory 195576 kb
Host smart-8c0518f2-97fd-4caf-98ce-30e1d3041116
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442347640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.1442347640
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.3511276247
Short name T199
Test name
Test status
Simulation time 146076690 ps
CPU time 8.7 seconds
Started Aug 09 07:17:20 PM PDT 24
Finished Aug 09 07:17:29 PM PDT 24
Peak memory 199780 kb
Host smart-d2a4b022-0a12-497b-a22d-46b08dc01885
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3511276247 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.3511276247
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.836733012
Short name T92
Test name
Test status
Simulation time 12994299838 ps
CPU time 49.43 seconds
Started Aug 09 07:17:25 PM PDT 24
Finished Aug 09 07:18:15 PM PDT 24
Peak memory 200044 kb
Host smart-39d8b49d-4ecf-4158-a8d4-a40fc4dea19c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836733012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.836733012
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.2839122343
Short name T403
Test name
Test status
Simulation time 12975916660 ps
CPU time 577.94 seconds
Started Aug 09 07:17:28 PM PDT 24
Finished Aug 09 07:27:06 PM PDT 24
Peak memory 680852 kb
Host smart-af2d1abb-b1ca-4f64-8f51-164ab7d501a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2839122343 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.2839122343
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.1943782325
Short name T415
Test name
Test status
Simulation time 16215016366 ps
CPU time 225.56 seconds
Started Aug 09 07:17:28 PM PDT 24
Finished Aug 09 07:21:14 PM PDT 24
Peak memory 200004 kb
Host smart-5293ce66-f263-4b54-9ede-9dd9085d491e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943782325 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.1943782325
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.577910395
Short name T295
Test name
Test status
Simulation time 2160163607 ps
CPU time 37.67 seconds
Started Aug 09 07:17:19 PM PDT 24
Finished Aug 09 07:17:57 PM PDT 24
Peak memory 199864 kb
Host smart-032702fe-470e-4711-ab43-24a186e08974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577910395 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.577910395
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.2622370925
Short name T520
Test name
Test status
Simulation time 150004040 ps
CPU time 7.02 seconds
Started Aug 09 07:17:21 PM PDT 24
Finished Aug 09 07:17:28 PM PDT 24
Peak memory 199824 kb
Host smart-43a9750f-a7ca-47ea-ac4c-0386cbba9389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622370925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.2622370925
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.4200790758
Short name T285
Test name
Test status
Simulation time 654508759 ps
CPU time 7.19 seconds
Started Aug 09 07:17:26 PM PDT 24
Finished Aug 09 07:17:33 PM PDT 24
Peak memory 199840 kb
Host smart-716f09c7-5966-4a72-8050-a0a55d65eba2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200790758 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.4200790758
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.2654783504
Short name T201
Test name
Test status
Simulation time 20327665464 ps
CPU time 88.77 seconds
Started Aug 09 07:17:34 PM PDT 24
Finished Aug 09 07:19:03 PM PDT 24
Peak memory 199848 kb
Host smart-c78e486f-8335-45c1-828d-843697f1dbef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654783504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.2654783504
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.395673218
Short name T228
Test name
Test status
Simulation time 124476961 ps
CPU time 0.6 seconds
Started Aug 09 07:17:26 PM PDT 24
Finished Aug 09 07:17:27 PM PDT 24
Peak memory 195916 kb
Host smart-96cc3889-2aad-486e-a90b-7e461c623eef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395673218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.395673218
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.2866080871
Short name T91
Test name
Test status
Simulation time 330787385 ps
CPU time 18.9 seconds
Started Aug 09 07:17:29 PM PDT 24
Finished Aug 09 07:17:48 PM PDT 24
Peak memory 199744 kb
Host smart-9ab679aa-0262-4753-bea7-d5fa58ec660a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2866080871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.2866080871
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.539542779
Short name T324
Test name
Test status
Simulation time 172332102 ps
CPU time 2.72 seconds
Started Aug 09 07:17:34 PM PDT 24
Finished Aug 09 07:17:37 PM PDT 24
Peak memory 199840 kb
Host smart-ddc6bf8b-f8fc-4e2c-9d7f-155a71261bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539542779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.539542779
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.906598605
Short name T260
Test name
Test status
Simulation time 15511568664 ps
CPU time 904.65 seconds
Started Aug 09 07:17:27 PM PDT 24
Finished Aug 09 07:32:31 PM PDT 24
Peak memory 724992 kb
Host smart-f254310d-dd97-460b-b5e7-fd972928a076
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=906598605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.906598605
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.3737923102
Short name T240
Test name
Test status
Simulation time 665295096 ps
CPU time 2.7 seconds
Started Aug 09 07:17:26 PM PDT 24
Finished Aug 09 07:17:29 PM PDT 24
Peak memory 199648 kb
Host smart-d035eab5-d44d-4fc3-88ed-2d291dc653af
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737923102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.3737923102
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.1463049838
Short name T215
Test name
Test status
Simulation time 11846280093 ps
CPU time 149.49 seconds
Started Aug 09 07:17:35 PM PDT 24
Finished Aug 09 07:20:05 PM PDT 24
Peak memory 216188 kb
Host smart-7a5490d2-9db8-496b-8899-f8706bbb3b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463049838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.1463049838
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.3592725910
Short name T242
Test name
Test status
Simulation time 882544680 ps
CPU time 14.28 seconds
Started Aug 09 07:17:26 PM PDT 24
Finished Aug 09 07:17:40 PM PDT 24
Peak memory 199824 kb
Host smart-ce317f5c-1d83-412a-81d1-0a2f41af64b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592725910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.3592725910
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.3012058222
Short name T470
Test name
Test status
Simulation time 77302708042 ps
CPU time 1590.33 seconds
Started Aug 09 07:17:29 PM PDT 24
Finished Aug 09 07:43:59 PM PDT 24
Peak memory 690988 kb
Host smart-dd4d322a-2a4c-4504-a442-b606cbfb5639
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012058222 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.3012058222
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.915200444
Short name T208
Test name
Test status
Simulation time 38975698244 ps
CPU time 119.65 seconds
Started Aug 09 07:17:28 PM PDT 24
Finished Aug 09 07:19:28 PM PDT 24
Peak memory 199936 kb
Host smart-c9fe2f71-a7fc-4cad-ad67-09e80b276f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915200444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.915200444
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.667662803
Short name T256
Test name
Test status
Simulation time 31915072 ps
CPU time 0.6 seconds
Started Aug 09 07:17:27 PM PDT 24
Finished Aug 09 07:17:28 PM PDT 24
Peak memory 195924 kb
Host smart-953d56a9-5996-4534-aca3-f8b30928ea87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667662803 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.667662803
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.3534631322
Short name T349
Test name
Test status
Simulation time 3342132711 ps
CPU time 94.98 seconds
Started Aug 09 07:17:28 PM PDT 24
Finished Aug 09 07:19:03 PM PDT 24
Peak memory 199940 kb
Host smart-02808815-da94-4130-aa49-68e9ebc6f5b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3534631322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.3534631322
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.2696055806
Short name T518
Test name
Test status
Simulation time 17177325445 ps
CPU time 59.66 seconds
Started Aug 09 07:17:28 PM PDT 24
Finished Aug 09 07:18:28 PM PDT 24
Peak memory 208084 kb
Host smart-d503e4a8-0acd-4d6d-9b6d-87f1bcef2c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696055806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.2696055806
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.2692450415
Short name T337
Test name
Test status
Simulation time 3605751081 ps
CPU time 126.98 seconds
Started Aug 09 07:17:29 PM PDT 24
Finished Aug 09 07:19:36 PM PDT 24
Peak memory 409084 kb
Host smart-8e41dbc8-89ca-4f56-b1b9-2b26e1efedc0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2692450415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.2692450415
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.1919978176
Short name T88
Test name
Test status
Simulation time 25109454984 ps
CPU time 249.78 seconds
Started Aug 09 07:17:35 PM PDT 24
Finished Aug 09 07:21:45 PM PDT 24
Peak memory 199848 kb
Host smart-5677a162-1f97-496f-af60-c16bf0d5f024
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919978176 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.1919978176
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.3062187913
Short name T315
Test name
Test status
Simulation time 8113204803 ps
CPU time 60.98 seconds
Started Aug 09 07:17:25 PM PDT 24
Finished Aug 09 07:18:26 PM PDT 24
Peak memory 199844 kb
Host smart-381dadeb-f8d7-4ffa-8307-633ba7f36343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062187913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.3062187913
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.234400591
Short name T289
Test name
Test status
Simulation time 817889878 ps
CPU time 10.33 seconds
Started Aug 09 07:17:27 PM PDT 24
Finished Aug 09 07:17:38 PM PDT 24
Peak memory 199840 kb
Host smart-bba566b6-5354-4978-ba45-ec7d1fdbd03e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234400591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.234400591
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.2211082245
Short name T334
Test name
Test status
Simulation time 508279562884 ps
CPU time 2653.21 seconds
Started Aug 09 07:17:26 PM PDT 24
Finished Aug 09 08:01:40 PM PDT 24
Peak memory 765104 kb
Host smart-dc49a182-5c38-4683-b960-0c4b1a95eaba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211082245 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.2211082245
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.2661291001
Short name T272
Test name
Test status
Simulation time 1028263675 ps
CPU time 25.83 seconds
Started Aug 09 07:17:26 PM PDT 24
Finished Aug 09 07:17:52 PM PDT 24
Peak memory 199820 kb
Host smart-ff30736d-3219-4f2f-a116-7728d5a5b1e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661291001 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.2661291001
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.3472817814
Short name T152
Test name
Test status
Simulation time 12611896 ps
CPU time 0.57 seconds
Started Aug 09 07:17:38 PM PDT 24
Finished Aug 09 07:17:38 PM PDT 24
Peak memory 194916 kb
Host smart-35e92dd5-9233-42e4-a312-75c7b4072170
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472817814 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.3472817814
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.1797717115
Short name T408
Test name
Test status
Simulation time 736128066 ps
CPU time 20.79 seconds
Started Aug 09 07:17:29 PM PDT 24
Finished Aug 09 07:17:50 PM PDT 24
Peak memory 199804 kb
Host smart-60468844-e7cd-4042-b177-2fccfb99b37c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1797717115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.1797717115
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.3906037252
Short name T261
Test name
Test status
Simulation time 4548319647 ps
CPU time 16.6 seconds
Started Aug 09 07:17:27 PM PDT 24
Finished Aug 09 07:17:43 PM PDT 24
Peak memory 199972 kb
Host smart-20356fa6-ccf5-4232-a594-964fa91d96e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906037252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.3906037252
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.3575079474
Short name T492
Test name
Test status
Simulation time 25303097961 ps
CPU time 1144.92 seconds
Started Aug 09 07:17:26 PM PDT 24
Finished Aug 09 07:36:31 PM PDT 24
Peak memory 737700 kb
Host smart-d2701b0d-29dc-43fc-a227-84e803b9ca11
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3575079474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.3575079474
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.2938092547
Short name T74
Test name
Test status
Simulation time 7217608694 ps
CPU time 125.78 seconds
Started Aug 09 07:17:26 PM PDT 24
Finished Aug 09 07:19:32 PM PDT 24
Peak memory 199816 kb
Host smart-b2e4f583-f23d-4191-859e-592802871278
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938092547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.2938092547
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.3207553637
Short name T266
Test name
Test status
Simulation time 14505734336 ps
CPU time 228.03 seconds
Started Aug 09 07:17:26 PM PDT 24
Finished Aug 09 07:21:14 PM PDT 24
Peak memory 199928 kb
Host smart-119e97f7-5617-4a82-8e16-5145cad1a7dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207553637 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.3207553637
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.4067531630
Short name T39
Test name
Test status
Simulation time 477984989 ps
CPU time 10.92 seconds
Started Aug 09 07:17:34 PM PDT 24
Finished Aug 09 07:17:45 PM PDT 24
Peak memory 199792 kb
Host smart-0841bfd0-4ce0-4512-a6aa-b7ba7ee02444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067531630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.4067531630
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.616308836
Short name T410
Test name
Test status
Simulation time 386039540571 ps
CPU time 1941.43 seconds
Started Aug 09 07:17:39 PM PDT 24
Finished Aug 09 07:50:01 PM PDT 24
Peak memory 680600 kb
Host smart-a8fc566b-9db8-47d7-b5e3-f05a79e1244c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616308836 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.616308836
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.3631089114
Short name T347
Test name
Test status
Simulation time 4746049695 ps
CPU time 24.29 seconds
Started Aug 09 07:17:34 PM PDT 24
Finished Aug 09 07:17:59 PM PDT 24
Peak memory 199956 kb
Host smart-436c7da7-1b10-4f4c-b1ab-e76ee5b4331a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631089114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.3631089114
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.2739355380
Short name T475
Test name
Test status
Simulation time 15100656 ps
CPU time 0.62 seconds
Started Aug 09 07:17:34 PM PDT 24
Finished Aug 09 07:17:35 PM PDT 24
Peak memory 195712 kb
Host smart-ead6927e-61ce-4607-ac09-3b6a8fea8cb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739355380 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.2739355380
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.175507344
Short name T45
Test name
Test status
Simulation time 2000293127 ps
CPU time 59.11 seconds
Started Aug 09 07:17:36 PM PDT 24
Finished Aug 09 07:18:35 PM PDT 24
Peak memory 199768 kb
Host smart-f46d4829-9eab-4f58-b3a8-0dcc5d2f7db2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=175507344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.175507344
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.881143470
Short name T512
Test name
Test status
Simulation time 1968457875 ps
CPU time 49.39 seconds
Started Aug 09 07:17:34 PM PDT 24
Finished Aug 09 07:18:23 PM PDT 24
Peak memory 199848 kb
Host smart-8a06f01a-8aa2-4005-8781-804075e45099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881143470 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.881143470
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.2741994782
Short name T211
Test name
Test status
Simulation time 7872548379 ps
CPU time 342.01 seconds
Started Aug 09 07:17:34 PM PDT 24
Finished Aug 09 07:23:17 PM PDT 24
Peak memory 685032 kb
Host smart-0e12fb62-923a-4eb6-9ff3-53f444cf81cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2741994782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.2741994782
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.2162401433
Short name T245
Test name
Test status
Simulation time 546890686 ps
CPU time 30.35 seconds
Started Aug 09 07:17:36 PM PDT 24
Finished Aug 09 07:18:06 PM PDT 24
Peak memory 199716 kb
Host smart-da7512c5-a657-414f-9b99-7f1cbef8b4d9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162401433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.2162401433
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.2815026698
Short name T303
Test name
Test status
Simulation time 26602820426 ps
CPU time 93.66 seconds
Started Aug 09 07:17:37 PM PDT 24
Finished Aug 09 07:19:11 PM PDT 24
Peak memory 199984 kb
Host smart-05dcc032-6a37-4387-aa7d-ef238c1ef74c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815026698 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.2815026698
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.255072427
Short name T325
Test name
Test status
Simulation time 914512554 ps
CPU time 12.58 seconds
Started Aug 09 07:17:37 PM PDT 24
Finished Aug 09 07:17:50 PM PDT 24
Peak memory 199836 kb
Host smart-e8605cb1-5ade-4193-b59c-aea468bfed67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255072427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.255072427
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.4186934876
Short name T216
Test name
Test status
Simulation time 214272766281 ps
CPU time 907.86 seconds
Started Aug 09 07:17:35 PM PDT 24
Finished Aug 09 07:32:43 PM PDT 24
Peak memory 208068 kb
Host smart-624b0180-c774-4e74-bce0-747ca278d9eb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186934876 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.4186934876
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.2266449867
Short name T198
Test name
Test status
Simulation time 6034019134 ps
CPU time 102.05 seconds
Started Aug 09 07:17:43 PM PDT 24
Finished Aug 09 07:19:25 PM PDT 24
Peak memory 199976 kb
Host smart-0e05a2ad-38a7-4f2b-af91-8b1eba93d27a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266449867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.2266449867
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.2388883986
Short name T252
Test name
Test status
Simulation time 17268792 ps
CPU time 0.58 seconds
Started Aug 09 07:17:35 PM PDT 24
Finished Aug 09 07:17:36 PM PDT 24
Peak memory 195904 kb
Host smart-1ca025c8-ef39-4c44-a33a-b08e4c92062a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388883986 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.2388883986
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.727726261
Short name T292
Test name
Test status
Simulation time 132721075 ps
CPU time 7.87 seconds
Started Aug 09 07:17:35 PM PDT 24
Finished Aug 09 07:17:43 PM PDT 24
Peak memory 199776 kb
Host smart-0568164f-0bce-4717-90b4-9ec4385ddec5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=727726261 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.727726261
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.1266929118
Short name T378
Test name
Test status
Simulation time 8517370564 ps
CPU time 26.3 seconds
Started Aug 09 07:17:35 PM PDT 24
Finished Aug 09 07:18:01 PM PDT 24
Peak memory 199912 kb
Host smart-dcd64e6f-8bde-4f49-9d9e-1e6e5b1e7aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266929118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.1266929118
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.2925667606
Short name T163
Test name
Test status
Simulation time 71210186 ps
CPU time 5.1 seconds
Started Aug 09 07:17:35 PM PDT 24
Finished Aug 09 07:17:40 PM PDT 24
Peak memory 199884 kb
Host smart-ecc6408a-29f7-404f-afed-e072134baeb0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2925667606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.2925667606
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.796050403
Short name T153
Test name
Test status
Simulation time 595755883 ps
CPU time 8.38 seconds
Started Aug 09 07:17:38 PM PDT 24
Finished Aug 09 07:17:46 PM PDT 24
Peak memory 199724 kb
Host smart-690fabd7-5e3d-4dfb-9542-63b6d3a05f58
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796050403 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.796050403
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.1191192934
Short name T384
Test name
Test status
Simulation time 15042596524 ps
CPU time 180.48 seconds
Started Aug 09 07:17:38 PM PDT 24
Finished Aug 09 07:20:38 PM PDT 24
Peak memory 200068 kb
Host smart-c5cd53ff-397e-4c4a-a78c-a26a6957c30d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191192934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.1191192934
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.270483400
Short name T3
Test name
Test status
Simulation time 74664133 ps
CPU time 3.26 seconds
Started Aug 09 07:17:42 PM PDT 24
Finished Aug 09 07:17:45 PM PDT 24
Peak memory 199952 kb
Host smart-486dc46b-e3da-4420-8e9d-6a432aec6385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270483400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.270483400
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.2369768146
Short name T462
Test name
Test status
Simulation time 30039955340 ps
CPU time 5237.76 seconds
Started Aug 09 07:17:35 PM PDT 24
Finished Aug 09 08:44:53 PM PDT 24
Peak memory 863220 kb
Host smart-f34d238f-14b5-48e8-add9-28a86752b1fb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369768146 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.2369768146
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.3755949943
Short name T162
Test name
Test status
Simulation time 1023121109 ps
CPU time 10.18 seconds
Started Aug 09 07:17:35 PM PDT 24
Finished Aug 09 07:17:45 PM PDT 24
Peak memory 199796 kb
Host smart-4ef3061b-b2b5-47dc-8380-4ef5b8c2859c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755949943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.3755949943
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.465011591
Short name T52
Test name
Test status
Simulation time 14216748 ps
CPU time 0.59 seconds
Started Aug 09 07:16:04 PM PDT 24
Finished Aug 09 07:16:05 PM PDT 24
Peak memory 195940 kb
Host smart-8ef998bf-1ac0-4d7d-bfb0-012f03923e13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465011591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.465011591
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.1115704503
Short name T416
Test name
Test status
Simulation time 2679477358 ps
CPU time 38.34 seconds
Started Aug 09 07:16:13 PM PDT 24
Finished Aug 09 07:16:52 PM PDT 24
Peak memory 199880 kb
Host smart-7d80f42d-2112-4483-9db6-858260fe8bba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1115704503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.1115704503
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.3153699240
Short name T421
Test name
Test status
Simulation time 22356268551 ps
CPU time 69.45 seconds
Started Aug 09 07:16:24 PM PDT 24
Finished Aug 09 07:17:33 PM PDT 24
Peak memory 216332 kb
Host smart-5f6165cc-9fbc-4499-84bf-fd8cf7f80348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153699240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.3153699240
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.3904463514
Short name T430
Test name
Test status
Simulation time 366384880 ps
CPU time 28.54 seconds
Started Aug 09 07:16:11 PM PDT 24
Finished Aug 09 07:16:40 PM PDT 24
Peak memory 251480 kb
Host smart-5ceb52e7-1ff5-4a62-aea4-852a3be5e85e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3904463514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.3904463514
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.629153266
Short name T443
Test name
Test status
Simulation time 43681005883 ps
CPU time 184.55 seconds
Started Aug 09 07:16:22 PM PDT 24
Finished Aug 09 07:19:27 PM PDT 24
Peak memory 199912 kb
Host smart-1879dd75-8cba-43e0-bb3a-0b7a67324dc1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629153266 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.629153266
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.815668293
Short name T138
Test name
Test status
Simulation time 2944898992 ps
CPU time 165.1 seconds
Started Aug 09 07:16:05 PM PDT 24
Finished Aug 09 07:18:55 PM PDT 24
Peak memory 199844 kb
Host smart-9913775b-ed9a-404d-97b6-a37569ab6543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815668293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.815668293
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.1977581609
Short name T521
Test name
Test status
Simulation time 1791984010 ps
CPU time 6.27 seconds
Started Aug 09 07:16:13 PM PDT 24
Finished Aug 09 07:16:20 PM PDT 24
Peak memory 199812 kb
Host smart-b9159f83-1708-4f5a-8375-b0ffedf820a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977581609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.1977581609
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.2163212379
Short name T87
Test name
Test status
Simulation time 103060459385 ps
CPU time 3606.33 seconds
Started Aug 09 07:16:15 PM PDT 24
Finished Aug 09 08:16:22 PM PDT 24
Peak memory 818344 kb
Host smart-dad9251e-3e7c-4eee-98a7-dc7ea0485a02
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163212379 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.2163212379
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.4056204787
Short name T333
Test name
Test status
Simulation time 8456229728 ps
CPU time 50.43 seconds
Started Aug 09 07:16:04 PM PDT 24
Finished Aug 09 07:16:54 PM PDT 24
Peak memory 199976 kb
Host smart-90141a37-b83d-4d8a-a226-2a97c657d42f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056204787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.4056204787
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.4208679212
Short name T459
Test name
Test status
Simulation time 15871132 ps
CPU time 0.59 seconds
Started Aug 09 07:16:11 PM PDT 24
Finished Aug 09 07:16:12 PM PDT 24
Peak memory 195920 kb
Host smart-505c123d-bbcf-414b-9122-711beccc548b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208679212 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.4208679212
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.2151551616
Short name T179
Test name
Test status
Simulation time 3972147556 ps
CPU time 51.43 seconds
Started Aug 09 07:16:12 PM PDT 24
Finished Aug 09 07:17:04 PM PDT 24
Peak memory 199988 kb
Host smart-9995082a-7801-41c2-9ba1-5ce1c05fa9cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2151551616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.2151551616
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.2201567091
Short name T46
Test name
Test status
Simulation time 1034349158 ps
CPU time 27.22 seconds
Started Aug 09 07:16:26 PM PDT 24
Finished Aug 09 07:16:54 PM PDT 24
Peak memory 199772 kb
Host smart-8854dcdc-f868-4c48-be4e-b9c1165fdddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201567091 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.2201567091
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.3147805156
Short name T202
Test name
Test status
Simulation time 1754043910 ps
CPU time 303.76 seconds
Started Aug 09 07:16:26 PM PDT 24
Finished Aug 09 07:21:30 PM PDT 24
Peak memory 617932 kb
Host smart-0e81321b-00df-4e56-af78-56409a203a17
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3147805156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.3147805156
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.3691143669
Short name T460
Test name
Test status
Simulation time 6853507998 ps
CPU time 41.46 seconds
Started Aug 09 07:16:03 PM PDT 24
Finished Aug 09 07:16:44 PM PDT 24
Peak memory 199936 kb
Host smart-00e86aa0-f52c-4754-b418-6778c496840e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691143669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.3691143669
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.1285825353
Short name T250
Test name
Test status
Simulation time 5688330474 ps
CPU time 97.24 seconds
Started Aug 09 07:16:08 PM PDT 24
Finished Aug 09 07:17:46 PM PDT 24
Peak memory 200092 kb
Host smart-53bf4dc5-4b89-4a1b-b4a7-da06589e9af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285825353 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.1285825353
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.2167098431
Short name T340
Test name
Test status
Simulation time 147694728 ps
CPU time 2.33 seconds
Started Aug 09 07:16:04 PM PDT 24
Finished Aug 09 07:16:06 PM PDT 24
Peak memory 199824 kb
Host smart-8bcd89ac-3737-4115-a419-66b97bbb3467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167098431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.2167098431
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all_with_rand_reset.1148175424
Short name T20
Test name
Test status
Simulation time 349729582378 ps
CPU time 2195.99 seconds
Started Aug 09 07:16:13 PM PDT 24
Finished Aug 09 07:52:49 PM PDT 24
Peak memory 763204 kb
Host smart-e8d48513-96da-4161-8199-7a90b7f74f65
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1148175424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all_with_rand_reset.1148175424
Directory /workspace/6.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.3612717667
Short name T28
Test name
Test status
Simulation time 5391061378 ps
CPU time 99.28 seconds
Started Aug 09 07:16:04 PM PDT 24
Finished Aug 09 07:17:43 PM PDT 24
Peak memory 199976 kb
Host smart-60e4a13b-8bea-409b-88df-933529ca362a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612717667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.3612717667
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.1507093475
Short name T291
Test name
Test status
Simulation time 46681650 ps
CPU time 0.63 seconds
Started Aug 09 07:16:22 PM PDT 24
Finished Aug 09 07:16:23 PM PDT 24
Peak memory 196600 kb
Host smart-c641189a-7726-47dc-b679-954b36343d67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507093475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.1507093475
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.3528722414
Short name T499
Test name
Test status
Simulation time 3623246396 ps
CPU time 108.89 seconds
Started Aug 09 07:16:26 PM PDT 24
Finished Aug 09 07:18:15 PM PDT 24
Peak memory 199876 kb
Host smart-aa53cb0f-ef35-4e6b-ac39-4125ae6c5940
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3528722414 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.3528722414
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.2910294405
Short name T59
Test name
Test status
Simulation time 14937293096 ps
CPU time 70.12 seconds
Started Aug 09 07:16:02 PM PDT 24
Finished Aug 09 07:17:12 PM PDT 24
Peak memory 208048 kb
Host smart-0e6d1f77-25af-4f8b-bb48-3d18949285ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910294405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.2910294405
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.2934969899
Short name T254
Test name
Test status
Simulation time 93084994 ps
CPU time 0.89 seconds
Started Aug 09 07:16:15 PM PDT 24
Finished Aug 09 07:16:16 PM PDT 24
Peak memory 210064 kb
Host smart-b9e8c671-813b-438a-9e48-fa11a777bab8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2934969899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.2934969899
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.630745963
Short name T264
Test name
Test status
Simulation time 15734570979 ps
CPU time 220.57 seconds
Started Aug 09 07:16:13 PM PDT 24
Finished Aug 09 07:19:54 PM PDT 24
Peak memory 199812 kb
Host smart-4a270b0c-525b-405d-8f37-15a235f4aa8a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630745963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.630745963
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.3667784843
Short name T271
Test name
Test status
Simulation time 124894933251 ps
CPU time 144.99 seconds
Started Aug 09 07:16:16 PM PDT 24
Finished Aug 09 07:18:41 PM PDT 24
Peak memory 199920 kb
Host smart-bd195d01-c532-4231-a563-73747476231f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667784843 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.3667784843
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.613338878
Short name T204
Test name
Test status
Simulation time 284574708 ps
CPU time 4.04 seconds
Started Aug 09 07:16:03 PM PDT 24
Finished Aug 09 07:16:07 PM PDT 24
Peak memory 199868 kb
Host smart-b6c63194-77c1-48f8-9003-d3ad02c7d501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613338878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.613338878
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.197864463
Short name T85
Test name
Test status
Simulation time 30986246167 ps
CPU time 257.33 seconds
Started Aug 09 07:16:21 PM PDT 24
Finished Aug 09 07:20:38 PM PDT 24
Peak memory 199892 kb
Host smart-ceb0a739-2640-444c-a8bc-76c7f16d967b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197864463 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.197864463
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_stress_all_with_rand_reset.1198566714
Short name T71
Test name
Test status
Simulation time 183037758443 ps
CPU time 834.91 seconds
Started Aug 09 07:16:29 PM PDT 24
Finished Aug 09 07:30:24 PM PDT 24
Peak memory 497932 kb
Host smart-ffc1a445-6092-4d9c-b8a0-1c1acee23f98
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1198566714 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all_with_rand_reset.1198566714
Directory /workspace/7.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.2232449712
Short name T165
Test name
Test status
Simulation time 951391219 ps
CPU time 17.08 seconds
Started Aug 09 07:16:25 PM PDT 24
Finished Aug 09 07:16:42 PM PDT 24
Peak memory 199772 kb
Host smart-8f6bd214-af35-4fdd-bd94-11ed0e8bd13f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232449712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.2232449712
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.1355019977
Short name T246
Test name
Test status
Simulation time 12333312 ps
CPU time 0.6 seconds
Started Aug 09 07:16:20 PM PDT 24
Finished Aug 09 07:16:20 PM PDT 24
Peak memory 196628 kb
Host smart-c0a05ec0-fb64-4b92-b490-fe81cb53ad7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355019977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.1355019977
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.3098086495
Short name T361
Test name
Test status
Simulation time 2425859841 ps
CPU time 70.04 seconds
Started Aug 09 07:16:22 PM PDT 24
Finished Aug 09 07:17:32 PM PDT 24
Peak memory 199864 kb
Host smart-dbabb088-12c4-4c2d-85ce-cf4772912fa6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3098086495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.3098086495
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.1467289499
Short name T209
Test name
Test status
Simulation time 429636481 ps
CPU time 7.72 seconds
Started Aug 09 07:16:20 PM PDT 24
Finished Aug 09 07:16:28 PM PDT 24
Peak memory 199804 kb
Host smart-5d09d520-0a74-4206-b4ff-7e7bbb0f0d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467289499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.1467289499
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.2986414239
Short name T203
Test name
Test status
Simulation time 2686311064 ps
CPU time 489.05 seconds
Started Aug 09 07:16:20 PM PDT 24
Finished Aug 09 07:24:29 PM PDT 24
Peak memory 511772 kb
Host smart-e9cb151d-5693-4a74-88cc-cfbf07329b4b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2986414239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.2986414239
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.3366369012
Short name T397
Test name
Test status
Simulation time 44036342985 ps
CPU time 135.05 seconds
Started Aug 09 07:16:22 PM PDT 24
Finished Aug 09 07:18:37 PM PDT 24
Peak memory 200100 kb
Host smart-62a65c08-983d-48b0-b859-809506d4bdb9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366369012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.3366369012
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.3730735426
Short name T477
Test name
Test status
Simulation time 8259862593 ps
CPU time 119.46 seconds
Started Aug 09 07:16:26 PM PDT 24
Finished Aug 09 07:18:25 PM PDT 24
Peak memory 199884 kb
Host smart-e6de3420-2625-46b0-910b-c4262d4bdc8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730735426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.3730735426
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.27586045
Short name T147
Test name
Test status
Simulation time 215440642 ps
CPU time 3.28 seconds
Started Aug 09 07:16:16 PM PDT 24
Finished Aug 09 07:16:20 PM PDT 24
Peak memory 199836 kb
Host smart-19f178f1-320b-4803-88e6-53565d719ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27586045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.27586045
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.3489209765
Short name T142
Test name
Test status
Simulation time 9697765146 ps
CPU time 515.99 seconds
Started Aug 09 07:16:23 PM PDT 24
Finished Aug 09 07:24:59 PM PDT 24
Peak memory 199896 kb
Host smart-fba315ea-53da-46bb-a9ad-d6dc831c47bc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489209765 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.3489209765
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_stress_all_with_rand_reset.410769560
Short name T70
Test name
Test status
Simulation time 33029589165 ps
CPU time 760.44 seconds
Started Aug 09 07:16:17 PM PDT 24
Finished Aug 09 07:28:58 PM PDT 24
Peak memory 609812 kb
Host smart-4ee93669-404d-46f9-b827-b9944eb5e4b2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=410769560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all_with_rand_reset.410769560
Directory /workspace/8.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.536758388
Short name T160
Test name
Test status
Simulation time 3741151949 ps
CPU time 47.28 seconds
Started Aug 09 07:16:24 PM PDT 24
Finished Aug 09 07:17:11 PM PDT 24
Peak memory 199936 kb
Host smart-13dd167c-a525-43e8-962d-26f6a6630699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536758388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.536758388
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.1878138658
Short name T398
Test name
Test status
Simulation time 23301920 ps
CPU time 0.61 seconds
Started Aug 09 07:16:16 PM PDT 24
Finished Aug 09 07:16:17 PM PDT 24
Peak memory 195928 kb
Host smart-4851d3a8-f358-4e29-b8c9-5bdcdb242171
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878138658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.1878138658
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.2370981272
Short name T24
Test name
Test status
Simulation time 3173555303 ps
CPU time 43.92 seconds
Started Aug 09 07:16:23 PM PDT 24
Finished Aug 09 07:17:07 PM PDT 24
Peak memory 199892 kb
Host smart-3f9a82a3-1557-435f-a97d-9bd82a28d214
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2370981272 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.2370981272
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.2475995752
Short name T280
Test name
Test status
Simulation time 2276550013 ps
CPU time 17.95 seconds
Started Aug 09 07:16:18 PM PDT 24
Finished Aug 09 07:16:36 PM PDT 24
Peak memory 199964 kb
Host smart-735f3de8-d985-4bc0-a8ca-191e978bcbf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475995752 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.2475995752
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.3199153800
Short name T433
Test name
Test status
Simulation time 4460379135 ps
CPU time 868.39 seconds
Started Aug 09 07:16:20 PM PDT 24
Finished Aug 09 07:30:49 PM PDT 24
Peak memory 717772 kb
Host smart-d78147bc-a97b-4147-b69a-061c1b5cf21f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3199153800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.3199153800
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.960947016
Short name T528
Test name
Test status
Simulation time 15271472632 ps
CPU time 50.79 seconds
Started Aug 09 07:16:18 PM PDT 24
Finished Aug 09 07:17:09 PM PDT 24
Peak memory 199916 kb
Host smart-0c98afa3-ccf4-4ba0-b715-d4b04b8688de
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960947016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.960947016
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.2252710902
Short name T274
Test name
Test status
Simulation time 21043386035 ps
CPU time 33.17 seconds
Started Aug 09 07:16:27 PM PDT 24
Finished Aug 09 07:17:01 PM PDT 24
Peak memory 199860 kb
Host smart-367389d6-ed86-4613-a514-1009ee6f8638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252710902 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.2252710902
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.351441211
Short name T438
Test name
Test status
Simulation time 634742795 ps
CPU time 10.03 seconds
Started Aug 09 07:16:24 PM PDT 24
Finished Aug 09 07:16:35 PM PDT 24
Peak memory 199772 kb
Host smart-5ebea5f9-67c0-4606-a955-df02b694241a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351441211 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.351441211
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.3006832028
Short name T86
Test name
Test status
Simulation time 87939864930 ps
CPU time 2441.03 seconds
Started Aug 09 07:16:17 PM PDT 24
Finished Aug 09 07:56:59 PM PDT 24
Peak memory 783196 kb
Host smart-ee313c63-564c-4698-a9e2-8f5fb20fc223
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006832028 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.3006832028
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_stress_all_with_rand_reset.1895835988
Short name T72
Test name
Test status
Simulation time 58343857310 ps
CPU time 1995.19 seconds
Started Aug 09 07:16:26 PM PDT 24
Finished Aug 09 07:49:41 PM PDT 24
Peak memory 686936 kb
Host smart-fc3d3dcc-f2e8-4c89-87bf-c3ed2779af26
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1895835988 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all_with_rand_reset.1895835988
Directory /workspace/9.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.2659580536
Short name T73
Test name
Test status
Simulation time 4924756744 ps
CPU time 42.02 seconds
Started Aug 09 07:16:21 PM PDT 24
Finished Aug 09 07:17:03 PM PDT 24
Peak memory 199896 kb
Host smart-79cd49a9-6505-4d59-9a2b-a0533209bc27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659580536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.2659580536
Directory /workspace/9.hmac_wipe_secret/latest
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