Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

51217184

1

T1

48581

T2

10617

T3

5

full_word

44567548

1

T1

39224

T2

8504

T3

4

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	95784262	1			T1	87805		T2	19121		T3	9
auto[TlIntgErrCmd]	163	1			T62	4		T63	11		T64	3
auto[TlIntgErrData]	131	1			T62	4		T63	7		T64	3
auto[TlIntgErrBoth]	176	1			T62	12		T63	12		T64	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

44808310

1

T1

44090

T2

9545

T3

1

auto[1]

50976422

1

T1

43715

T2

9576

T3

8

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	23289125	1			T1	22004		T2	4742		T4	55582
auto[TlIntgErrNone]	partial	auto[1]	27927623	1			T1	26577		T2	5875		T3	5
auto[TlIntgErrNone]	full_word	auto[0]	21518983	1			T1	22086		T2	4803		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	23048531	1			T1	17138		T2	3701		T3	3
auto[TlIntgErrCmd]	partial	auto[0]	60	1			T62	1		T63	3		T64	1
auto[TlIntgErrCmd]	partial	auto[1]	88	1			T62	2		T63	7		T64	2
auto[TlIntgErrCmd]	full_word	auto[0]	8	1			T62	1		T63	1		T113	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T113	1		T115	1		T116	1
auto[TlIntgErrData]	partial	auto[0]	63	1			T62	1		T63	2		T64	2
auto[TlIntgErrData]	partial	auto[1]	62	1			T62	3		T63	4		T64	1
auto[TlIntgErrData]	full_word	auto[0]	2	1			T114	1		T117	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	4	1			T63	1		T118	1		T119	1
auto[TlIntgErrBoth]	partial	auto[0]	62	1			T62	4		T63	7		T64	1
auto[TlIntgErrBoth]	partial	auto[1]	101	1			T62	6		T63	5		T64	2
auto[TlIntgErrBoth]	full_word	auto[0]	7	1			T62	1		T113	2		T115	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T62	1		T64	1		T115	1