Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00	93.33	100.00	100.00	98.90	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	521786902	2554284	0	0
intr_enable_rd_A	521786902	4039	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521786902	2554284	0	0
T9	281490	53681	0	0
T10	137640	24486	0	0
T11	0	133789	0	0
T20	0	305094	0	0
T21	0	362002	0	0
T22	0	382845	0	0
T24	141302	0	0	0
T39	224084	0	0	0
T40	104409	0	0	0
T41	225281	0	0	0
T42	688935	0	0	0
T43	43686	0	0	0
T60	0	332720	0	0
T65	0	103107	0	0
T66	0	121260	0	0
T67	0	83241	0	0
T68	353759	0	0	0
T69	85095	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521786902	4039	0	0
T11	0	101	0	0
T70	165435	79	0	0
T71	916904	17	0	0
T72	0	35	0	0
T73	0	132	0	0
T74	0	14	0	0
T75	0	47	0	0
T76	0	37	0	0
T77	0	18	0	0
T78	0	38	0	0
T79	746061	0	0	0
T80	76232	0	0	0
T81	169899	0	0	0
T82	68805	0	0	0
T83	110637	0	0	0
T84	383009	0	0	0
T85	255102	0	0	0
T86	2461	0	0	0