Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	40430642	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

38714854

1

T1

105640

T2

39844

T3

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	37595862	1			T1	120323		T2	45044		T3	1
values[0x0]	19492995	1			T1	54951		T2	20492		T3	4
values[0x1]	22056639	1			T1	64382		T2	24202		T3	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	31106533	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

48038963

1

T1

136259

T2

51254

T3

3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	242666	1			T1	602		T2	579		T5	50
valid_sources[0x01]	252611	1			T1	1513		T2	254		T5	36
valid_sources[0x02]	240551	1			T1	388		T2	170		T5	50
valid_sources[0x03]	241283	1			T1	1004		T2	49		T5	30
valid_sources[0x04]	245744	1			T1	607		T2	251		T5	41
valid_sources[0x05]	243925	1			T1	2058		T2	179		T5	26
valid_sources[0x06]	246661	1			T1	645		T2	389		T5	56
valid_sources[0x07]	330265	1			T1	2039		T2	305		T5	47
valid_sources[0x08]	274582	1			T1	837		T2	1216		T5	37
valid_sources[0x09]	243792	1			T1	1389		T2	37		T5	28
valid_sources[0x0a]	244632	1			T1	1344		T2	162		T5	26
valid_sources[0x0b]	292170	1			T1	2242		T2	177		T5	29
valid_sources[0x0c]	244293	1			T1	1492		T2	195		T5	34
valid_sources[0x0d]	243086	1			T1	1705		T2	445		T5	39
valid_sources[0x0e]	247355	1			T1	787		T2	522		T5	31
valid_sources[0x0f]	244925	1			T1	792		T2	497		T5	33
valid_sources[0x10]	241943	1			T1	1051		T2	62		T5	38
valid_sources[0x11]	255257	1			T1	1131		T2	224		T5	30
valid_sources[0x12]	245990	1			T1	1432		T2	100		T5	29
valid_sources[0x13]	245887	1			T1	1194		T2	670		T5	28
valid_sources[0x14]	298552	1			T1	906		T5	37		T15	29
valid_sources[0x15]	313088	1			T1	570		T2	10		T5	24
valid_sources[0x16]	246621	1			T1	677		T2	116		T5	39
valid_sources[0x17]	244617	1			T1	696		T2	78		T5	36
valid_sources[0x18]	246964	1			T1	1471		T2	225		T3	1
valid_sources[0x19]	244233	1			T1	1538		T2	253		T5	37
valid_sources[0x1a]	242710	1			T1	1099		T2	292		T5	31
valid_sources[0x1b]	333643	1			T1	371		T2	249		T5	35
valid_sources[0x1c]	242683	1			T1	526		T2	686		T5	40
valid_sources[0x1d]	309771	1			T1	603		T2	217		T5	36
valid_sources[0x1e]	242290	1			T1	635		T2	197		T5	39
valid_sources[0x1f]	299875	1			T1	477		T2	76		T5	35
valid_sources[0x20]	464786	1			T1	325		T2	29		T5	37
valid_sources[0x21]	244192	1			T1	1261		T2	57		T5	46
valid_sources[0x22]	244248	1			T1	183		T2	51		T5	28
valid_sources[0x23]	246235	1			T1	754		T2	26		T5	32
valid_sources[0x24]	243486	1			T1	1067		T2	427		T5	35
valid_sources[0x25]	245114	1			T1	1648		T2	251		T5	29
valid_sources[0x26]	2641195	1			T1	1082		T2	407		T5	41
valid_sources[0x27]	264580	1			T1	977		T2	603		T5	26
valid_sources[0x28]	246226	1			T1	762		T5	35		T15	50
valid_sources[0x29]	269217	1			T1	1065		T2	458		T5	59
valid_sources[0x2a]	247925	1			T1	758		T2	797		T5	26
valid_sources[0x2b]	246521	1			T1	644		T2	328		T5	37
valid_sources[0x2c]	249688	1			T1	1139		T2	16		T5	40
valid_sources[0x2d]	243753	1			T1	527		T2	899		T5	53
valid_sources[0x2e]	242547	1			T1	1081		T2	175		T5	32
valid_sources[0x2f]	409700	1			T1	1831		T2	366		T5	44
valid_sources[0x30]	351967	1			T1	695		T2	158		T5	43
valid_sources[0x31]	266134	1			T1	674		T2	450		T5	35
valid_sources[0x32]	279851	1			T1	580		T2	779		T5	31
valid_sources[0x33]	242304	1			T1	344		T2	76		T5	44
valid_sources[0x34]	563823	1			T1	430		T2	569		T5	47
valid_sources[0x35]	242861	1			T1	231		T2	392		T5	26
valid_sources[0x36]	390086	1			T1	655		T2	89		T5	29
valid_sources[0x37]	264736	1			T1	763		T2	457		T5	30
valid_sources[0x38]	256251	1			T1	1189		T2	213		T5	25
valid_sources[0x39]	242863	1			T1	857		T2	594		T5	33
valid_sources[0x3a]	245114	1			T1	731		T2	96		T5	40
valid_sources[0x3b]	281627	1			T1	601		T2	235		T5	47
valid_sources[0x3c]	283208	1			T1	1659		T2	35		T5	36
valid_sources[0x3d]	249352	1			T1	1907		T2	450		T5	40
valid_sources[0x3e]	241602	1			T1	595		T2	75		T5	40
valid_sources[0x3f]	244307	1			T1	1986		T2	21		T5	42
valid_sources[0x40]	248004	1			T1	1252		T2	338		T5	44
valid_sources[0x41]	510992	1			T1	1171		T2	550		T5	39
valid_sources[0x42]	2281690	1			T1	1021		T2	70		T5	47
valid_sources[0x43]	243238	1			T1	378		T2	327		T5	49
valid_sources[0x44]	240974	1			T1	1007		T2	331		T5	23
valid_sources[0x45]	333426	1			T1	578		T2	103		T5	33
valid_sources[0x46]	267992	1			T1	911		T2	314		T5	53
valid_sources[0x47]	242206	1			T1	843		T2	483		T5	33
valid_sources[0x48]	244765	1			T1	1478		T2	54		T5	39
valid_sources[0x49]	258545	1			T1	987		T2	545		T3	2
valid_sources[0x4a]	246603	1			T1	376		T2	470		T5	29
valid_sources[0x4b]	244789	1			T1	966		T2	759		T5	38
valid_sources[0x4c]	270299	1			T1	964		T2	761		T5	40
valid_sources[0x4d]	251168	1			T1	1284		T2	923		T5	34
valid_sources[0x4e]	244522	1			T1	975		T2	6		T5	40
valid_sources[0x4f]	250169	1			T1	1254		T2	352		T5	40
valid_sources[0x50]	245174	1			T1	1041		T2	429		T5	44
valid_sources[0x51]	346338	1			T1	1314		T2	98		T5	32
valid_sources[0x52]	276018	1			T1	1025		T2	293		T5	32
valid_sources[0x53]	242650	1			T1	594		T5	29		T15	52
valid_sources[0x54]	246776	1			T1	1896		T5	45		T15	39
valid_sources[0x55]	243507	1			T1	473		T2	433		T5	50
valid_sources[0x56]	330199	1			T1	1106		T2	1022		T5	43
valid_sources[0x57]	248794	1			T1	1113		T5	32		T15	48
valid_sources[0x58]	240866	1			T1	844		T2	192		T5	37
valid_sources[0x59]	266253	1			T1	1019		T2	363		T5	38
valid_sources[0x5a]	243606	1			T1	897		T2	470		T5	42
valid_sources[0x5b]	242129	1			T1	1074		T2	62		T5	54
valid_sources[0x5c]	244757	1			T1	995		T2	443		T5	42
valid_sources[0x5d]	249142	1			T1	796		T2	468		T5	40
valid_sources[0x5e]	244372	1			T1	684		T2	723		T5	47
valid_sources[0x5f]	246173	1			T1	1441		T2	44		T5	24
valid_sources[0x60]	487383	1			T1	1359		T2	321		T5	27
valid_sources[0x61]	252132	1			T1	828		T2	601		T5	37
valid_sources[0x62]	244470	1			T1	632		T2	26		T5	30
valid_sources[0x63]	256297	1			T1	1384		T2	496		T5	46
valid_sources[0x64]	246548	1			T1	854		T2	667		T5	47
valid_sources[0x65]	346040	1			T1	583		T2	93		T5	29
valid_sources[0x66]	335530	1			T1	777		T2	80		T5	40
valid_sources[0x67]	337596	1			T1	556		T2	108		T5	33
valid_sources[0x68]	254701	1			T1	825		T2	95		T5	38
valid_sources[0x69]	239634	1			T1	947		T2	107		T5	33
valid_sources[0x6a]	242289	1			T1	238		T2	3		T5	44
valid_sources[0x6b]	530114	1			T1	686		T2	635		T5	37
valid_sources[0x6c]	468475	1			T1	697		T2	213		T5	39
valid_sources[0x6d]	241840	1			T1	1117		T2	467		T5	38
valid_sources[0x6e]	243906	1			T1	493		T2	245		T5	42
valid_sources[0x6f]	367556	1			T1	734		T2	532		T5	45
valid_sources[0x70]	423168	1			T1	1267		T2	110		T5	34
valid_sources[0x71]	244838	1			T1	1063		T2	53		T5	44
valid_sources[0x72]	245313	1			T1	1407		T2	98		T5	45
valid_sources[0x73]	243753	1			T1	368		T2	14		T5	38
valid_sources[0x74]	244309	1			T1	708		T2	155		T5	43
valid_sources[0x75]	247991	1			T1	726		T2	271		T5	29
valid_sources[0x76]	275865	1			T1	1619		T2	250		T5	28
valid_sources[0x77]	245046	1			T1	1036		T5	36		T15	49
valid_sources[0x78]	246250	1			T1	452		T2	116		T5	26
valid_sources[0x79]	241928	1			T1	1017		T2	46		T5	33
valid_sources[0x7a]	248354	1			T1	1173		T2	282		T5	38
valid_sources[0x7b]	247901	1			T1	1281		T2	346		T5	38
valid_sources[0x7c]	241537	1			T1	267		T2	182		T5	39
valid_sources[0x7d]	501578	1			T1	670		T2	403		T5	35
valid_sources[0x7e]	258674	1			T1	1719		T2	517		T5	36
valid_sources[0x7f]	306668	1			T1	1145		T2	144		T5	36
valid_sources[0x80]	244767	1			T1	753		T2	43		T5	49

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

18582872

1

T1

60109

T2

22521

T3

1

values[0x0]

all_enables

biggest_size

10827212

1

T1

25230

T2

9570

T5

1383

values[0x1]

all_enables

biggest_size

9304770

1

T1

20301

T2

7753

T3

2