Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

43613121

1

T1

134016

T2

49894

T3

4

full_word

38920851

1

T1

105640

T2

39844

T3

3

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	82533592	1			T1	239656		T2	89738		T3	7
auto[TlIntgErrCmd]	137	1			T61	4		T62	9		T63	8
auto[TlIntgErrData]	117	1			T61	1		T62	6		T63	7
auto[TlIntgErrBoth]	126	1			T61	5		T62	5		T63	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

38646787

1

T1

120323

T2

45044

T3

1

auto[1]

43887185

1

T1

119333

T2

44694

T3

6

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	19983484	1			T1	60214		T2	22523		T5	2619
auto[TlIntgErrNone]	partial	auto[1]	23629285	1			T1	73802		T2	27371		T3	4
auto[TlIntgErrNone]	full_word	auto[0]	18663128	1			T1	60109		T2	22521		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	20257695	1			T1	45531		T2	17323		T3	2
auto[TlIntgErrCmd]	partial	auto[0]	58	1			T61	1		T62	5		T63	1
auto[TlIntgErrCmd]	partial	auto[1]	71	1			T61	3		T62	4		T63	7
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T121	1		T122	1		T64	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T123	1		T120	1		T124	1
auto[TlIntgErrData]	partial	auto[0]	47	1			T62	5		T63	2		T118	2
auto[TlIntgErrData]	partial	auto[1]	56	1			T61	1		T62	1		T63	3
auto[TlIntgErrData]	full_word	auto[0]	7	1			T63	2		T125	1		T126	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T118	1		T127	1		T124	1
auto[TlIntgErrBoth]	partial	auto[0]	56	1			T61	1		T62	2		T63	3
auto[TlIntgErrBoth]	partial	auto[1]	64	1			T61	4		T62	3		T63	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T118	1		T125	1		T128	2
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T120	1		T128	1		-	-