Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00	93.33	100.00	100.00	98.90	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	447348738	1848928	0	0
intr_enable_rd_A	447348738	3072	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447348738	1848928	0	0
T8	628234	87800	0	0
T9	0	388400	0	0
T10	0	219468	0	0
T14	0	24692	0	0
T19	144279	0	0	0
T25	0	50309	0	0
T65	0	210327	0	0
T66	0	55318	0	0
T67	0	34041	0	0
T68	0	45813	0	0
T69	0	9340	0	0
T70	735069	0	0	0
T71	537792	0	0	0
T72	123177	0	0	0
T73	158921	0	0	0
T74	355582	0	0	0
T75	359912	0	0	0
T76	400275	0	0	0
T77	242456	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447348738	3072	0	0
T8	628234	180	0	0
T10	0	295	0	0
T14	0	37	0	0
T19	144279	0	0	0
T57	0	6	0	0
T68	0	76	0	0
T70	735069	0	0	0
T71	537792	0	0	0
T72	123177	0	0	0
T73	158921	0	0	0
T74	355582	0	0	0
T75	359912	0	0	0
T76	400275	0	0	0
T77	242456	0	0	0
T78	0	17	0	0
T79	0	40	0	0
T80	0	24	0	0
T81	0	23	0	0
T82	0	4	0	0