Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

39059707

1

T1

16

T2

13

T3

152111

full_word

35712057

1

T1

1

T2

4

T3

119762

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	74771324	1			T1	17		T2	17		T3	271873
auto[TlIntgErrCmd]	169	1			T61	9		T62	11		T63	6
auto[TlIntgErrData]	125	1			T61	7		T62	10		T63	7
auto[TlIntgErrBoth]	146	1			T61	4		T62	9		T63	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35593319

1

T1

1

T2

1

T3

136032

auto[1]

39178445

1

T1

16

T2

16

T3

135841

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	18110375	1			T1	1		T3	68160		T6	2831
auto[TlIntgErrNone]	partial	auto[1]	20948926	1			T1	15		T2	13		T3	83951
auto[TlIntgErrNone]	full_word	auto[0]	17482743	1			T2	1		T3	67872		T6	2908
auto[TlIntgErrNone]	full_word	auto[1]	18229280	1			T1	1		T2	3		T3	51890
auto[TlIntgErrCmd]	partial	auto[0]	69	1			T61	5		T62	4		T63	2
auto[TlIntgErrCmd]	partial	auto[1]	84	1			T61	4		T62	5		T63	4
auto[TlIntgErrCmd]	full_word	auto[0]	8	1			T62	1		T81	1		T128	2
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T62	1		T128	1		T130	2
auto[TlIntgErrData]	partial	auto[0]	57	1			T61	2		T62	3		T63	4
auto[TlIntgErrData]	partial	auto[1]	62	1			T61	4		T62	7		T63	3
auto[TlIntgErrData]	full_word	auto[0]	4	1			T61	1		T131	2		T64	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T129	1		T132	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	58	1			T61	1		T62	6		T63	1
auto[TlIntgErrBoth]	partial	auto[1]	76	1			T61	3		T62	3		T63	6
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T126	1		T133	1		T134	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T129	1		T130	2		T131	2