Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00	93.33	100.00	100.00	98.90	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	412818140	448158	0	0
intr_enable_rd_A	412818140	3904	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412818140	448158	0	0
T12	170794	6147	0	0
T13	0	10277	0	0
T14	0	7426	0	0
T18	0	2341	0	0
T23	0	13231	0	0
T35	89829	0	0	0
T36	142570	0	0	0
T37	174916	0	0	0
T38	165616	0	0	0
T39	471110	0	0	0
T61	0	7	0	0
T62	0	11	0	0
T63	0	5	0	0
T65	0	20105	0	0
T66	0	434	0	0
T67	108396	0	0	0
T68	393367	0	0	0
T69	303555	0	0	0
T70	106554	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412818140	3904	0	0
T9	71001	0	0	0
T13	0	43	0	0
T22	613667	0	0	0
T24	411245	44	0	0
T39	0	120	0	0
T42	236854	0	0	0
T43	124125	0	0	0
T44	0	67	0	0
T47	509412	0	0	0
T71	0	80	0	0
T72	0	31	0	0
T73	0	21	0	0
T74	0	29	0	0
T75	0	30	0	0
T76	0	27	0	0
T77	7971	0	0	0
T78	24299	0	0	0
T79	1103	0	0	0
T80	423155	0	0	0