Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

39947847

1

T1

10823

T2

39487

T3

568676

full_word

35617365

1

T1

16711

T2

32122

T3

571152

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	75564802	1			T1	27534		T2	71609		T3	113982
auto[TlIntgErrCmd]	155	1			T55	7		T56	4		T57	8
auto[TlIntgErrData]	115	1			T55	6		T56	8		T57	7
auto[TlIntgErrBoth]	140	1			T55	7		T56	8		T57	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35738905

1

T1

11275

T2

34092

T3

531843

auto[1]

39826307

1

T1

16259

T2

37517

T3

607985

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	18298189	1			T1	5704		T2	16988		T3	268336
auto[TlIntgErrNone]	partial	auto[1]	21649280	1			T1	5119		T2	22499		T3	300340
auto[TlIntgErrNone]	full_word	auto[0]	17440524	1			T1	5571		T2	17104		T3	263507
auto[TlIntgErrNone]	full_word	auto[1]	18176809	1			T1	11140		T2	15018		T3	307645
auto[TlIntgErrCmd]	partial	auto[0]	64	1			T55	1		T56	3		T57	1
auto[TlIntgErrCmd]	partial	auto[1]	79	1			T55	6		T56	1		T57	6
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T126	1		T127	1		T128	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T57	1		T121	1		T126	2
auto[TlIntgErrData]	partial	auto[0]	53	1			T55	2		T56	4		T57	4
auto[TlIntgErrData]	partial	auto[1]	49	1			T55	4		T56	3		T57	1
auto[TlIntgErrData]	full_word	auto[0]	7	1			T56	1		T121	1		T124	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T57	2		T126	1		T129	2
auto[TlIntgErrBoth]	partial	auto[0]	60	1			T55	1		T56	3		T57	3
auto[TlIntgErrBoth]	partial	auto[1]	73	1			T55	6		T56	5		T57	1
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T130	1		T131	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T57	1		T121	1		T126	1