Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00	93.33	100.00	100.00	98.90	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	449261948	1052940	0	0
intr_enable_rd_A	449261948	2844	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449261948	1052940	0	0
T4	355415	4112	0	0
T5	79733	0	0	0
T6	25695	0	0	0
T7	0	13558	0	0
T8	0	18522	0	0
T12	6252	0	0	0
T13	173461	0	0	0
T14	121635	0	0	0
T15	136086	0	0	0
T19	0	15931	0	0
T20	0	15485	0	0
T31	1017	0	0	0
T32	1168	0	0	0
T33	859	0	0	0
T58	0	2214	0	0
T59	0	1074	0	0
T60	0	16	0	0
T61	0	945	0	0
T62	0	28	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449261948	2844	0	0
T40	301338	8	0	0
T63	0	13	0	0
T64	0	23	0	0
T65	0	18	0	0
T66	0	64	0	0
T67	0	20	0	0
T68	0	43	0	0
T69	0	19	0	0
T70	0	27	0	0
T71	0	5	0	0
T72	578121	0	0	0
T73	286501	0	0	0
T74	76344	0	0	0
T75	176206	0	0	0
T76	210312	0	0	0
T77	28065	0	0	0
T78	551178	0	0	0
T79	391363	0	0	0
T80	898	0	0	0