Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	39530545	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

37077054

1

T1

69049

T2

46549

T3

164753

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	36571512	1			T1	70223		T2	52874		T3	188059
values[0x0]	18800782	1			T1	34632		T2	23999		T3	85491
values[0x1]	21235305	1			T1	38872		T2	28217		T3	101579

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	30498875	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

46108724

1

T1

86156

T2

59940

T3

213141

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	217055	1			T1	596		T3	1429		T4	50
valid_sources[0x01]	277860	1			T1	560		T3	1433		T4	55
valid_sources[0x02]	220819	1			T1	546		T3	1563		T4	53
valid_sources[0x03]	219939	1			T1	573		T3	1324		T4	50
valid_sources[0x04]	222741	1			T1	572		T3	1502		T4	73
valid_sources[0x05]	220479	1			T1	551		T3	1535		T4	71
valid_sources[0x06]	217204	1			T1	529		T3	1600		T4	54
valid_sources[0x07]	218158	1			T1	580		T3	1486		T4	44
valid_sources[0x08]	219394	1			T1	543		T3	1430		T4	45
valid_sources[0x09]	221576	1			T1	569		T3	1447		T4	56
valid_sources[0x0a]	224508	1			T1	585		T3	1569		T4	39
valid_sources[0x0b]	224247	1			T1	555		T3	1499		T4	34
valid_sources[0x0c]	257196	1			T1	567		T3	1388		T4	67
valid_sources[0x0d]	219054	1			T1	632		T3	1500		T4	70
valid_sources[0x0e]	219496	1			T1	568		T3	1516		T4	30
valid_sources[0x0f]	221996	1			T1	548		T3	1491		T4	66
valid_sources[0x10]	225764	1			T1	565		T3	1534		T4	44
valid_sources[0x11]	229426	1			T1	535		T3	1424		T4	55
valid_sources[0x12]	827137	1			T1	546		T3	1463		T4	52
valid_sources[0x13]	220747	1			T1	576		T3	1480		T4	66
valid_sources[0x14]	243616	1			T1	586		T3	1439		T4	48
valid_sources[0x15]	259253	1			T1	602		T3	1421		T4	80
valid_sources[0x16]	219428	1			T1	540		T3	1470		T4	54
valid_sources[0x17]	271391	1			T1	555		T3	1378		T4	66
valid_sources[0x18]	217117	1			T1	578		T3	1423		T4	54
valid_sources[0x19]	231349	1			T1	519		T3	1405		T4	39
valid_sources[0x1a]	218218	1			T1	530		T3	1422		T4	43
valid_sources[0x1b]	218485	1			T1	578		T3	1509		T4	47
valid_sources[0x1c]	252846	1			T1	547		T3	1430		T4	58
valid_sources[0x1d]	245480	1			T1	548		T3	1449		T4	63
valid_sources[0x1e]	218526	1			T1	580		T3	1512		T4	41
valid_sources[0x1f]	222790	1			T1	568		T3	1414		T4	52
valid_sources[0x20]	222025	1			T1	562		T3	1363		T4	43
valid_sources[0x21]	220130	1			T1	555		T3	1398		T4	57
valid_sources[0x22]	217885	1			T1	575		T3	1430		T4	40
valid_sources[0x23]	220691	1			T1	566		T3	1502		T4	69
valid_sources[0x24]	219221	1			T1	554		T3	1514		T4	47
valid_sources[0x25]	228150	1			T1	554		T3	1491		T4	24
valid_sources[0x26]	218630	1			T1	555		T3	1459		T4	29
valid_sources[0x27]	219273	1			T1	573		T3	1504		T4	55
valid_sources[0x28]	220211	1			T1	540		T3	1471		T4	59
valid_sources[0x29]	318378	1			T1	587		T3	1548		T4	44
valid_sources[0x2a]	218628	1			T1	597		T3	1489		T4	36
valid_sources[0x2b]	219421	1			T1	510		T3	1519		T4	67
valid_sources[0x2c]	219818	1			T1	482		T3	1473		T4	51
valid_sources[0x2d]	1031830	1			T1	560		T3	1580		T4	59
valid_sources[0x2e]	216990	1			T1	560		T3	1504		T4	49
valid_sources[0x2f]	222075	1			T1	541		T3	1459		T4	66
valid_sources[0x30]	220382	1			T1	556		T3	1443		T4	37
valid_sources[0x31]	243633	1			T1	560		T3	1528		T4	52
valid_sources[0x32]	558953	1			T1	545		T3	1475		T4	42
valid_sources[0x33]	289956	1			T1	527		T3	1442		T4	54
valid_sources[0x34]	218320	1			T1	602		T3	1451		T4	44
valid_sources[0x35]	397776	1			T1	577		T3	1484		T4	47
valid_sources[0x36]	217696	1			T1	529		T3	1476		T4	54
valid_sources[0x37]	300688	1			T1	505		T3	1377		T4	29
valid_sources[0x38]	219808	1			T1	571		T3	1402		T4	52
valid_sources[0x39]	218642	1			T1	592		T3	1492		T4	62
valid_sources[0x3a]	220023	1			T1	555		T3	1499		T4	60
valid_sources[0x3b]	421280	1			T1	577		T3	1490		T4	55
valid_sources[0x3c]	714811	1			T1	561		T3	1565		T4	45
valid_sources[0x3d]	1205237	1			T1	547		T3	1522		T4	67
valid_sources[0x3e]	217976	1			T1	576		T3	1417		T4	45
valid_sources[0x3f]	218483	1			T1	547		T3	1504		T4	48
valid_sources[0x40]	220085	1			T1	608		T3	1409		T4	27
valid_sources[0x41]	474155	1			T1	545		T3	1369		T4	57
valid_sources[0x42]	219212	1			T1	572		T3	1504		T4	47
valid_sources[0x43]	219221	1			T1	532		T3	1450		T4	66
valid_sources[0x44]	219279	1			T1	558		T3	1561		T4	62
valid_sources[0x45]	218535	1			T1	566		T3	1570		T4	104
valid_sources[0x46]	219085	1			T1	593		T3	1342		T4	44
valid_sources[0x47]	218160	1			T1	536		T3	1471		T4	61
valid_sources[0x48]	219876	1			T1	557		T3	1432		T4	62
valid_sources[0x49]	235586	1			T1	604		T3	1442		T4	32
valid_sources[0x4a]	220438	1			T1	556		T3	1432		T4	80
valid_sources[0x4b]	694526	1			T1	535		T3	1533		T4	67
valid_sources[0x4c]	226070	1			T1	585		T3	1554		T4	49
valid_sources[0x4d]	586010	1			T1	558		T3	1410		T4	47
valid_sources[0x4e]	260150	1			T1	536		T3	1530		T4	64
valid_sources[0x4f]	469964	1			T1	548		T3	1396		T4	62
valid_sources[0x50]	226093	1			T1	555		T3	1444		T4	82
valid_sources[0x51]	1584717	1			T1	599		T3	1505		T4	56
valid_sources[0x52]	219352	1			T1	590		T3	1445		T4	44
valid_sources[0x53]	592661	1			T1	564		T3	1544		T4	69
valid_sources[0x54]	255209	1			T1	540		T3	1460		T4	43
valid_sources[0x55]	219926	1			T1	532		T3	1448		T4	48
valid_sources[0x56]	219621	1			T1	515		T3	1571		T4	68
valid_sources[0x57]	435686	1			T1	593		T3	1485		T4	54
valid_sources[0x58]	219160	1			T1	582		T3	1397		T4	37
valid_sources[0x59]	221082	1			T1	564		T3	1463		T4	47
valid_sources[0x5a]	220543	1			T1	571		T3	1438		T4	49
valid_sources[0x5b]	232819	1			T1	544		T3	1418		T4	51
valid_sources[0x5c]	230620	1			T1	546		T3	1422		T4	49
valid_sources[0x5d]	228657	1			T1	536		T3	1475		T4	35
valid_sources[0x5e]	238623	1			T1	585		T3	1434		T4	71
valid_sources[0x5f]	219688	1			T1	591		T3	1471		T4	58
valid_sources[0x60]	217542	1			T1	574		T3	1435		T4	69
valid_sources[0x61]	218835	1			T1	525		T3	1430		T4	60
valid_sources[0x62]	218623	1			T1	574		T3	1467		T4	43
valid_sources[0x63]	303085	1			T1	523		T3	1459		T4	54
valid_sources[0x64]	217899	1			T1	607		T3	1504		T4	70
valid_sources[0x65]	303782	1			T1	550		T3	1433		T4	57
valid_sources[0x66]	215928	1			T1	601		T3	1469		T4	80
valid_sources[0x67]	218390	1			T1	532		T3	1479		T4	71
valid_sources[0x68]	600965	1			T1	545		T3	1507		T4	64
valid_sources[0x69]	219731	1			T1	596		T3	1403		T4	59
valid_sources[0x6a]	220621	1			T1	535		T3	1537		T4	40
valid_sources[0x6b]	218008	1			T1	515		T3	1450		T4	59
valid_sources[0x6c]	219423	1			T1	589		T3	1478		T4	54
valid_sources[0x6d]	218955	1			T1	590		T3	1365		T4	58
valid_sources[0x6e]	588505	1			T1	553		T3	1500		T4	52
valid_sources[0x6f]	320332	1			T1	589		T3	1553		T4	44
valid_sources[0x70]	216920	1			T1	586		T3	1379		T4	59
valid_sources[0x71]	258275	1			T1	551		T3	1424		T4	56
valid_sources[0x72]	222943	1			T1	563		T3	1498		T4	40
valid_sources[0x73]	219241	1			T1	571		T3	1445		T4	45
valid_sources[0x74]	219389	1			T1	526		T3	1499		T4	36
valid_sources[0x75]	293315	1			T1	558		T3	1507		T4	55
valid_sources[0x76]	219299	1			T1	561		T3	1441		T4	33
valid_sources[0x77]	220159	1			T1	581		T3	1485		T4	53
valid_sources[0x78]	220581	1			T1	560		T3	1419		T4	56
valid_sources[0x79]	220757	1			T1	588		T3	1481		T4	53
valid_sources[0x7a]	218428	1			T1	578		T3	1431		T4	56
valid_sources[0x7b]	258378	1			T1	544		T3	1497		T4	39
valid_sources[0x7c]	220535	1			T1	602		T3	1399		T4	47
valid_sources[0x7d]	220064	1			T1	559		T3	1446		T4	58
valid_sources[0x7e]	219573	1			T1	544		T3	1437		T4	50
valid_sources[0x7f]	218610	1			T1	576		T3	1557		T4	47
valid_sources[0x80]	248085	1			T1	611		T3	1470		T4	62

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

18051026

1

T1

35189

T2

26409

T3

94007

values[0x0]

all_enables

biggest_size

10266568

1

T1

18393

T2

11122

T3

39135

values[0x1]

all_enables

biggest_size

8759460

1

T1

15467

T2

9018

T3

31611