Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

40373119

1

T1

74678

T2

58541

T3

210376

full_word

37131808

1

T1

69049

T2

46549

T3

164753

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	77504537	1			T1	143727		T2	105090		T3	375129
auto[TlIntgErrCmd]	144	1			T70	8		T71	8		T72	3
auto[TlIntgErrData]	120	1			T70	8		T71	12		T72	5
auto[TlIntgErrBoth]	126	1			T70	4		T71	10		T72	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

36853634

1

T1

70223

T2

52874

T3

188059

auto[1]

40651293

1

T1

73504

T2

52216

T3

187070

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	18781120	1			T1	35034		T2	26465		T3	94052
auto[TlIntgErrNone]	partial	auto[1]	21591644	1			T1	39644		T2	32076		T3	116324
auto[TlIntgErrNone]	full_word	auto[0]	18072334	1			T1	35189		T2	26409		T3	94007
auto[TlIntgErrNone]	full_word	auto[1]	19059439	1			T1	33860		T2	20140		T3	70746
auto[TlIntgErrCmd]	partial	auto[0]	59	1			T70	5		T71	1		T72	1
auto[TlIntgErrCmd]	partial	auto[1]	72	1			T70	3		T71	7		T147	3
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T72	2		T154	1		T149	2
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T154	1		T151	1		T148	1
auto[TlIntgErrData]	partial	auto[0]	55	1			T70	4		T71	5		T72	3
auto[TlIntgErrData]	partial	auto[1]	52	1			T70	3		T71	6		T72	2
auto[TlIntgErrData]	full_word	auto[0]	7	1			T70	1		T148	1		T150	2
auto[TlIntgErrData]	full_word	auto[1]	6	1			T71	1		T154	1		T155	1
auto[TlIntgErrBoth]	partial	auto[0]	48	1			T70	1		T71	3		T72	1
auto[TlIntgErrBoth]	partial	auto[1]	69	1			T70	3		T71	6		T72	1
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T71	1		T147	2		T156	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T155	1		T149	2		-	-