Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00	93.33	100.00	100.00	98.90	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	388227922	487635	0	0
intr_enable_rd_A	388227922	2690	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388227922	487635	0	0
T9	850951	4390	0	0
T10	0	23088	0	0
T11	0	12529	0	0
T70	0	6	0	0
T71	0	6	0	0
T75	0	322	0	0
T76	0	6	0	0
T77	0	570	0	0
T78	0	8	0	0
T79	0	192	0	0
T80	32016	0	0	0
T81	912877	0	0	0
T82	55766	0	0	0
T83	230342	0	0	0
T84	182769	0	0	0
T85	815725	0	0	0
T86	212861	0	0	0
T87	487424	0	0	0
T88	387612	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388227922	2690	0	0
T27	788063	80	0	0
T57	1429	0	0	0
T59	256587	0	0	0
T89	0	22	0	0
T90	0	7	0	0
T91	0	29	0	0
T92	0	80	0	0
T93	0	47	0	0
T94	0	103	0	0
T95	0	26	0	0
T96	0	12	0	0
T97	0	47	0	0
T98	470689	0	0	0
T99	39520	0	0	0
T100	182664	0	0	0
T101	115499	0	0	0
T102	51323	0	0	0
T103	464631	0	0	0
T104	269810	0	0	0