Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

38942703

1

T1

22822

T2

5623

T3

54123

full_word

36018998

1

T1

35625

T2

6037

T3

42853

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	74961291	1			T1	58447		T2	11660		T3	96976
auto[TlIntgErrCmd]	141	1			T65	7		T66	6		T67	8
auto[TlIntgErrData]	145	1			T65	7		T66	4		T67	8
auto[TlIntgErrBoth]	124	1			T65	6		T67	4		T143	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35551999

1

T1

24113

T2

6050

T3

48625

auto[1]

39409702

1

T1

34334

T2

5610

T3

48351

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	18112875	1			T1	12334		T2	3128		T3	24340
auto[TlIntgErrNone]	partial	auto[1]	20829456	1			T1	10488		T2	2495		T3	29783
auto[TlIntgErrNone]	full_word	auto[0]	17438944	1			T1	11779		T2	2922		T3	24285
auto[TlIntgErrNone]	full_word	auto[1]	18580016	1			T1	23846		T2	3115		T3	18568
auto[TlIntgErrCmd]	partial	auto[0]	55	1			T65	5		T66	2		T67	2
auto[TlIntgErrCmd]	partial	auto[1]	74	1			T65	2		T66	2		T67	5
auto[TlIntgErrCmd]	full_word	auto[0]	8	1			T66	1		T67	1		T144	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T66	1		T143	1		T146	1
auto[TlIntgErrData]	partial	auto[0]	67	1			T65	3		T66	1		T67	5
auto[TlIntgErrData]	partial	auto[1]	67	1			T65	3		T66	3		T67	3
auto[TlIntgErrData]	full_word	auto[0]	3	1			T65	1		T149	1		T150	1
auto[TlIntgErrData]	full_word	auto[1]	8	1			T151	2		T152	2		T153	3
auto[TlIntgErrBoth]	partial	auto[0]	43	1			T65	1		T67	1		T143	2
auto[TlIntgErrBoth]	partial	auto[1]	66	1			T65	4		T67	3		T143	6
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T144	1		T154	1		T148	1
auto[TlIntgErrBoth]	full_word	auto[1]	11	1			T65	1		T143	1		T154	1