Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00	93.33	100.00	100.00	98.90	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	372131001	471484	0	0
intr_enable_rd_A	372131001	2514	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372131001	471484	0	0
T6	684275	5025	0	0
T7	0	15628	0	0
T8	0	6000	0	0
T13	0	12913	0	0
T18	35069	0	0	0
T28	1094	0	0	0
T29	784646	0	0	0
T30	396006	0	0	0
T31	407763	0	0	0
T32	37418	0	0	0
T33	1506	0	0	0
T65	0	6	0	0
T66	0	1	0	0
T70	0	8454	0	0
T71	0	1154	0	0
T72	0	729	0	0
T73	0	471	0	0
T74	109223	0	0	0
T75	544717	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372131001	2514	0	0
T13	0	68	0	0
T36	0	30	0	0
T69	709232	43	0	0
T76	0	29	0	0
T77	0	45	0	0
T78	0	36	0	0
T79	0	4	0	0
T80	0	24	0	0
T81	0	22	0	0
T82	0	9	0	0
T83	712	0	0	0
T84	13214	0	0	0
T85	513652	0	0	0
T86	79975	0	0	0
T87	12017	0	0	0
T88	374387	0	0	0
T89	160123	0	0	0
T90	594586	0	0	0
T91	59167	0	0	0