Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

41562614

1

T1

10937

T2

9

T3

50434

full_word

38061749

1

T1

9013

T2

2

T3

39536

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	79623953	1			T1	19950		T2	11		T3	89970
auto[TlIntgErrCmd]	155	1			T56	3		T57	8		T58	2
auto[TlIntgErrData]	135	1			T56	2		T57	4		T58	2
auto[TlIntgErrBoth]	120	1			T56	5		T57	8		T58	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

37645714

1

T1

10050

T2

1

T3

45118

auto[1]

41978649

1

T1

9900

T2

10

T3

44852

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	19241125	1			T1	4958		T2	1		T3	22658
auto[TlIntgErrNone]	partial	auto[1]	22321123	1			T1	5979		T2	8		T3	27776
auto[TlIntgErrNone]	full_word	auto[0]	18404422	1			T1	5092		T3	22460		T6	6724
auto[TlIntgErrNone]	full_word	auto[1]	19657283	1			T1	3921		T2	2		T3	17076
auto[TlIntgErrCmd]	partial	auto[0]	59	1			T57	3		T116	6		T118	3
auto[TlIntgErrCmd]	partial	auto[1]	81	1			T56	2		T57	4		T58	2
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T56	1		T118	1		T59	2
auto[TlIntgErrCmd]	full_word	auto[1]	10	1			T57	1		T60	1		T119	1
auto[TlIntgErrData]	partial	auto[0]	46	1			T56	1		T57	2		T116	1
auto[TlIntgErrData]	partial	auto[1]	71	1			T57	1		T58	2		T116	4
auto[TlIntgErrData]	full_word	auto[0]	8	1			T57	1		T60	1		T120	1
auto[TlIntgErrData]	full_word	auto[1]	10	1			T56	1		T60	1		T121	3
auto[TlIntgErrBoth]	partial	auto[0]	44	1			T57	4		T58	1		T116	7
auto[TlIntgErrBoth]	partial	auto[1]	65	1			T56	4		T57	4		T58	5
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T120	1		T122	1		T119	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T56	1		T60	1		T120	2