Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00	93.33	100.00	100.00	98.90	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	446479867	925087	0	0
intr_enable_rd_A	446479867	3502	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446479867	925087	0	0
T9	346026	4646	0	0
T10	0	24769	0	0
T11	0	6027	0	0
T15	0	1433	0	0
T16	0	6455	0	0
T19	107242	0	0	0
T22	0	6830	0	0
T39	574233	0	0	0
T57	0	2	0	0
T61	0	19	0	0
T62	0	362	0	0
T63	0	373	0	0
T64	496543	0	0	0
T65	91585	0	0	0
T66	148763	0	0	0
T67	27924	0	0	0
T68	522940	0	0	0
T69	1021	0	0	0
T70	2291	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446479867	3502	0	0
T11	0	64	0	0
T20	115130	9	0	0
T21	198971	0	0	0
T36	260474	0	0	0
T40	102651	0	0	0
T42	102604	0	0	0
T71	0	46	0	0
T72	0	13	0	0
T73	0	26	0	0
T74	0	38	0	0
T75	0	21	0	0
T76	0	10	0	0
T77	0	38	0	0
T78	0	27	0	0
T79	694681	0	0	0
T80	178003	0	0	0
T81	352725	0	0	0
T82	304863	0	0	0
T83	8134	0	0	0