SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[hmac_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 57386120 | 1 | T1 | 60562 | T2 | 342932 | T3 | 76 | ||||
auto[1] | 16929642 | 1 | T1 | 13380 | T2 | 124822 | T7 | 22120 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 74315500 | 1 | T1 | 73942 | T2 | 467754 | T3 | 76 | ||||
values[1] | 31 | 1 | T67 | 2 | T68 | 2 | T69 | 1 | ||||
values[2] | 3 | 1 | T124 | 1 | T125 | 1 | T126 | 1 | ||||
values[3] | 131 | 1 | T67 | 4 | T68 | 3 | T69 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 74315516 | 1 | T1 | 73942 | T2 | 467754 | T3 | 76 | ||||
values[1] | 33 | 1 | T67 | 3 | T68 | 3 | T69 | 1 | ||||
values[2] | 6 | 1 | T68 | 1 | T127 | 1 | T128 | 1 | ||||
values[3] | 102 | 1 | T67 | 7 | T68 | 8 | T69 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 74315372 | 1 | T1 | 73942 | T2 | 467754 | T3 | 76 | ||||
auto[TlIntgErrCmd] | 144 | 1 | T67 | 3 | T68 | 4 | T69 | 5 | ||||
auto[TlIntgErrData] | 128 | 1 | T67 | 12 | T68 | 9 | T69 | 2 | ||||
auto[TlIntgErrBoth] | 118 | 1 | T67 | 5 | T68 | 7 | T69 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |