Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

38723659

1

T1

37792

T2

229738

T3

27

full_word

35592103

1

T1

36150

T2

238016

T3

49

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	74315372	1			T1	73942		T2	467754		T3	76
auto[TlIntgErrCmd]	144	1			T67	3		T68	4		T69	5
auto[TlIntgErrData]	128	1			T67	12		T68	9		T69	2
auto[TlIntgErrBoth]	118	1			T67	5		T68	7		T69	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35408801

1

T1

36927

T2

223186

T3

39

auto[1]

38906961

1

T1

37015

T2

244568

T3

37

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	17983612	1			T1	18430		T2	120368		T3	23
auto[TlIntgErrNone]	partial	auto[1]	20739694	1			T1	19362		T2	109370		T3	4
auto[TlIntgErrNone]	full_word	auto[0]	17425025	1			T1	18497		T2	102818		T3	16
auto[TlIntgErrNone]	full_word	auto[1]	18167041	1			T1	17653		T2	135198		T3	33
auto[TlIntgErrCmd]	partial	auto[0]	57	1			T67	2		T68	2		T69	2
auto[TlIntgErrCmd]	partial	auto[1]	74	1			T67	1		T68	2		T69	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T69	1		T129	1		T130	2
auto[TlIntgErrCmd]	full_word	auto[1]	9	1			T128	2		T124	1		T131	1
auto[TlIntgErrData]	partial	auto[0]	57	1			T67	5		T68	5		T69	2
auto[TlIntgErrData]	partial	auto[1]	56	1			T67	6		T68	3		T127	4
auto[TlIntgErrData]	full_word	auto[0]	5	1			T68	1		T127	1		T131	1
auto[TlIntgErrData]	full_word	auto[1]	10	1			T67	1		T127	2		T132	2
auto[TlIntgErrBoth]	partial	auto[0]	37	1			T67	1		T127	3		T133	1
auto[TlIntgErrBoth]	partial	auto[1]	72	1			T67	3		T68	6		T69	3
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T67	1		T68	1		T134	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T129	2		T135	1		T136	1