Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00	93.33	100.00	100.00	98.90	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	416246726	350817	0	0
intr_enable_rd_A	416246726	2334	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416246726	350817	0	0
T9	368730	2983	0	0
T10	0	14794	0	0
T11	0	6655	0	0
T25	27694	0	0	0
T67	0	3	0	0
T68	0	10	0	0
T71	0	287	0	0
T72	0	11	0	0
T73	0	438	0	0
T74	0	1163	0	0
T75	0	1245	0	0
T76	32200	0	0	0
T77	28266	0	0	0
T78	88096	0	0	0
T79	20273	0	0	0
T80	623102	0	0	0
T81	16104	0	0	0
T82	211661	0	0	0
T83	62768	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416246726	2334	0	0
T5	483542	54	0	0
T6	179361	0	0	0
T8	171256	0	0	0
T11	0	53	0	0
T12	110615	0	0	0
T18	857	0	0	0
T22	954309	0	0	0
T23	136101	0	0	0
T39	0	21	0	0
T46	76574	0	0	0
T53	105687	0	0	0
T54	1274	0	0	0
T72	0	14	0	0
T84	0	11	0	0
T85	0	35	0	0
T86	0	38	0	0
T87	0	9	0	0
T88	0	23	0	0
T89	0	21	0	0