Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_cg_wrap::tl_intg_err_cg

Group : cip_base_pkg::tl_intg_err_cg_wrap::tl_intg_err_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group Instance tl_intg_err_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_mem	2	0	2	100.00	100	1	1	2
cp_num_cmd_err_bits	4	0	4	100.00	100	1	1	0
cp_num_data_err_bits	4	0	4	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0

Summary for Variable cp_is_mem

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_mem

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

58053423

1

T1

77596

T2

118541

T3

15651

auto[1]

17007191

1

T1

17283

T2

27359

T3

4865

---

Summary for Variable cp_num_cmd_err_bits

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_num_cmd_err_bits

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	75060330	1			T1	94879		T2	145900		T3	20516
values[1]	21	1			T56	2		T57	1		T58	2
values[2]	3	1			T116	1		T117	1		T118	1
values[3]	155	1			T56	12		T57	10		T58	8

---

Summary for Variable cp_num_data_err_bits

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_num_data_err_bits

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	75060363	1			T1	94879		T2	145900		T3	20516
values[1]	25	1			T56	2		T119	2		T120	1
values[2]	4	1			T121	1		T122	1		T123	1
values[3]	129	1			T56	10		T57	3		T58	8

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	75060204	1			T1	94879		T2	145900		T3	20516
auto[TlIntgErrCmd]	159	1			T56	12		T57	12		T58	8
auto[TlIntgErrData]	126	1			T56	5		T57	4		T58	6
auto[TlIntgErrBoth]	125	1			T56	13		T57	4		T58	6