Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

38826159

1

T1

48987

T2

76144

T3

11421

full_word

36234455

1

T1

45892

T2

69756

T3

9095

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	75060204	1			T1	94879		T2	145900		T3	20516
auto[TlIntgErrCmd]	159	1			T56	12		T57	12		T58	8
auto[TlIntgErrData]	126	1			T56	5		T57	4		T58	6
auto[TlIntgErrBoth]	125	1			T56	13		T57	4		T58	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35678949

1

T1

47260

T2

71520

T3

10355

auto[1]

39381665

1

T1

47619

T2

74380

T3

10161

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	18196780	1			T1	23616		T2	35760		T3	5261
auto[TlIntgErrNone]	partial	auto[1]	20629008	1			T1	25371		T2	40384		T3	6160
auto[TlIntgErrNone]	full_word	auto[0]	17481983	1			T1	23644		T2	35760		T3	5094
auto[TlIntgErrNone]	full_word	auto[1]	18752433	1			T1	22248		T2	33996		T3	4001
auto[TlIntgErrCmd]	partial	auto[0]	62	1			T56	5		T57	3		T58	3
auto[TlIntgErrCmd]	partial	auto[1]	86	1			T56	6		T57	8		T58	5
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T124	1		T125	2		T126	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T56	1		T57	1		T124	1
auto[TlIntgErrData]	partial	auto[0]	48	1			T56	1		T57	1		T58	5
auto[TlIntgErrData]	partial	auto[1]	65	1			T56	4		T57	3		T58	1
auto[TlIntgErrData]	full_word	auto[0]	11	1			T119	2		T125	1		T121	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T120	1		T117	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	53	1			T56	7		T57	1		T58	3
auto[TlIntgErrBoth]	partial	auto[1]	57	1			T56	5		T57	2		T58	2
auto[TlIntgErrBoth]	full_word	auto[0]	8	1			T57	1		T58	1		T119	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T56	1		T119	1		T126	3