Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00	93.33	100.00	100.00	98.90	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	416003739	476815	0	0
intr_enable_rd_A	416003739	2950	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416003739	476815	0	0
T8	522448	6342	0	0
T9	0	11139	0	0
T10	0	19687	0	0
T12	134086	0	0	0
T56	0	9	0	0
T57	0	4	0	0
T58	0	4	0	0
T60	0	13259	0	0
T61	0	16	0	0
T62	0	17	0	0
T63	0	173	0	0
T64	983036	0	0	0
T65	376645	0	0	0
T66	6456	0	0	0
T67	101938	0	0	0
T68	175214	0	0	0
T69	808152	0	0	0
T70	184640	0	0	0
T71	389731	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416003739	2950	0	0
T8	0	42	0	0
T17	62528	0	0	0
T18	116393	0	0	0
T33	686528	67	0	0
T36	1250	0	0	0
T40	102560	0	0	0
T49	0	14	0	0
T72	0	26	0	0
T73	0	16	0	0
T74	0	23	0	0
T75	0	35	0	0
T76	0	39	0	0
T77	0	25	0	0
T78	0	36	0	0
T79	296535	0	0	0
T80	146586	0	0	0
T81	31631	0	0	0
T82	709381	0	0	0
T83	116317	0	0	0