Unified Coverage Report :: Module :: prim_intr_hw

Module : prim_intr_hw

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.intr_hw_hmac_done	100.00	100.00	100.00			100.00	100.00
tb.dut.intr_hw_fifo_empty	100.00	100.00	100.00			100.00	100.00
tb.dut.intr_hw_hmac_err	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.intr_hw_hmac_done

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00	93.33	100.00	100.00	98.90	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.intr_hw_fifo_empty

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00	93.33	100.00	100.00	98.90	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.intr_hw_hmac_err

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00	93.33	100.00	100.00	98.90	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Event" )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.intr_hw_hmac_done

SCORE	LINE
100.00	100.00

tb.dut.intr_hw_hmac_err

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	67	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
ALWAYS	95	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62	1	1
64	1	1
67	1	1
69	1	1
95	1	1
96	1	1
98	1	1

---

Line Coverage for Module : prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Status" )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.intr_hw_fifo_empty

	Line No.	Total	Covered	Percent
TOTAL		10	10	100.00
ALWAYS	75	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
ALWAYS	95	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
75	2	2
76	2	2
			MISSING_ELSE
81	1	1
83	1	1
88	1	1
95	1	1
96	1	1
98	1	1

---

Cond Coverage for Module : prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Event" )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.intr_hw_hmac_done

SCORE	COND
100.00	100.00

tb.dut.intr_hw_hmac_err

	Total	Covered	Percent
Conditions	12	12	100.00
Logical	12	12	100.00
Non-Logical	0	0
Event	0	0

 LINE       62
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T33,T29,T59

 LINE       62
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T33,T29,T59
1	1	Covered	T33,T29,T59

 LINE       67
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Status" )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.intr_hw_fifo_empty

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T33,T29,T59
1	0	Covered	T16,T20,T28

 LINE       83
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T33,T29,T59
1	0	Covered	T16,T20,T28

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T33,T29,T59
1	1	Covered	T16,T33,T20

---

Branch Coverage for Module : prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Event" )
Branch Coverage for Module self-instances :

SCORE	BRANCH
100.00	100.00

tb.dut.intr_hw_hmac_done

SCORE	BRANCH
100.00	100.00

tb.dut.intr_hw_hmac_err

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	95	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	95	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Status" )
Branch Coverage for Module self-instances :

SCORE	BRANCH
100.00	100.00

tb.dut.intr_hw_fifo_empty

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	75	3	3	100.00
IF	95	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	75	if ((!rst_ni))
-2-:	76	if (reg2hw_intr_test_qe_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T33,T29,T59
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	95	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_intr_hw

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IntrTKind_A	1464	1464	0	0

IntrTKind_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1464	1464	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T14	3	3	0	0
T15	3	3	0	0
T16	3	3	0	0

Line Coverage for Instance : tb.dut.intr_hw_hmac_done

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	67	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
ALWAYS	95	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62	1	1
64	1	1
67	1	1
69	1	1
95	1	1
96	1	1
98	1	1

---

Cond Coverage for Instance : tb.dut.intr_hw_hmac_done

	Total	Covered	Percent
Conditions	12	12	100.00
Logical	12	12	100.00
Non-Logical	0	0
Event	0	0

 LINE       62
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T33,T29,T59

 LINE       62
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T33,T29,T59
1	1	Covered	T33,T29,T59

 LINE       67
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T33,T114
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.intr_hw_hmac_done

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	95	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	95	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.intr_hw_hmac_done

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IntrTKind_A	488	488	0	0

IntrTKind_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488	488	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.intr_hw_fifo_empty

	Line No.	Total	Covered	Percent
TOTAL		10	10	100.00
ALWAYS	75	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
ALWAYS	95	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
75	2	2
76	2	2
			MISSING_ELSE
81	1	1
83	1	1
88	1	1
95	1	1
96	1	1
98	1	1

---

Cond Coverage for Instance : tb.dut.intr_hw_fifo_empty

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T33,T29,T59
1	0	Covered	T16,T20,T28

 LINE       83
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T33,T29,T59
1	0	Covered	T16,T20,T28

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T33,T29,T59
1	1	Covered	T16,T33,T20

---

Branch Coverage for Instance : tb.dut.intr_hw_fifo_empty

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	75	3	3	100.00
IF	95	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	75	if ((!rst_ni))
-2-:	76	if (reg2hw_intr_test_qe_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T33,T29,T59
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	95	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.intr_hw_fifo_empty

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IntrTKind_A	488	488	0	0

IntrTKind_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488	488	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.intr_hw_hmac_err

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	67	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
ALWAYS	95	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62	1	1
64	1	1
67	1	1
69	1	1
95	1	1
96	1	1
98	1	1

---

Cond Coverage for Instance : tb.dut.intr_hw_hmac_err

	Total	Covered	Percent
Conditions	12	12	100.00
Logical	12	12	100.00
Non-Logical	0	0
Event	0	0

 LINE       62
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T33,T29,T59

 LINE       62
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T33,T29,T59
1	1	Covered	T33,T29,T59

 LINE       67
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.intr_hw_hmac_err

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	95	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	95	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.intr_hw_hmac_err

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IntrTKind_A	488	488	0	0

IntrTKind_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488	488	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0