Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	17942950	1			T1	15032		T2	4569		T3	1664
all_values[1]	17942950	1			T1	15032		T2	4569		T3	1664
all_values[2]	17942950	1			T1	15032		T2	4569		T3	1664

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

219106

1

T3

191

T4

29

T15

1

auto[1]

53609744

1

T1

45096

T2

13707

T3

4801

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

45837332

1

T1

39587

T2

10736

T3

4455

auto[1]

7991518

1

T1

5509

T2

2971

T3

537

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	73577	1			T15	1		T18	88		T6	4
all_values[0]	auto[0]	auto[1]	413	1			T18	2		T6	2		T21	4
all_values[0]	auto[1]	auto[0]	17849434	1			T1	15013		T2	4566		T3	1658
all_values[0]	auto[1]	auto[1]	19526	1			T1	19		T2	3		T3	6
all_values[1]	auto[0]	auto[0]	92367	1			T4	28		T16	38		T6	3
all_values[1]	auto[0]	auto[1]	187	1			T6	2		T21	3		T19	6
all_values[1]	auto[1]	auto[0]	17850143	1			T1	15032		T2	4569		T3	1664
all_values[1]	auto[1]	auto[1]	253	1			T4	3		T6	4		T21	4
all_values[2]	auto[0]	auto[0]	28454	1			T17	53		T6	2		T21	6
all_values[2]	auto[0]	auto[1]	24108	1			T3	191		T4	1		T6	2
all_values[2]	auto[1]	auto[0]	9943357	1			T1	9542		T2	1601		T3	1133
all_values[2]	auto[1]	auto[1]	7947031	1			T1	5490		T2	2968		T3	340