Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	32	0	32	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len_lower_cp	15	0	15	100.00	100	1	1	0
msg_len_upper_cp	1	0	1	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_lower_cross	30	0	30	100.00	100	1	1	0
msg_len_upper_cross	2	0	2	100.00	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

124693

1

T1

30

T2

12

T3

8

auto[1]

124534

1

T1

18

T2

2

T3

6

---

Summary for Variable msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len_lower_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_2050_plus	94924	1			T1	19		T2	2		T3	4
len_1026_2046	5733	1			T4	47		T5	1		T16	2
len_514_1022	3453	1			T1	2		T4	15		T17	6
len_2_510	3613	1			T4	11		T18	2		T6	26
len_2056	262	1			T6	2		T127	1		T129	1
len_2048	367	1			T4	1		T18	1		T6	1
len_2040	187	1			T6	3		T19	4		T127	1
len_1032	438	1			T6	1		T19	5		T127	3
len_1024	1840	1			T4	4		T5	1		T16	3
len_1016	216	1			T4	2		T18	6		T6	1
len_520	178	1			T18	7		T19	3		T60	4
len_512	356	1			T4	2		T6	3		T21	6
len_504	195	1			T6	2		T19	3		T127	3
len_8	1282	1			T6	11		T21	61		T19	12
len_0	11569	1			T1	3		T2	5		T3	3

---

Summary for Variable msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for msg_len_upper_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

len_upper

107

1

T4

3

T5

4

T21

1

---

Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for msg_len_lower_cross

Bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	len_2050_plus	49343	1			T1	10		T2	1		T3	2
auto[0]	len_1026_2046	2709	1			T4	21		T17	4		T18	3
auto[0]	len_514_1022	2049	1			T1	2		T4	11		T17	5
auto[0]	len_2_510	2135	1			T4	9		T18	1		T6	5
auto[0]	len_2056	147	1			T6	2		T141	1		T9	2
auto[0]	len_2048	207	1			T4	1		T21	4		T19	4
auto[0]	len_2040	87	1			T6	2		T19	4		T127	1
auto[0]	len_1032	349	1			T6	1		T19	2		T127	3
auto[0]	len_1024	254	1			T4	4		T5	1		T16	2
auto[0]	len_1016	130	1			T4	2		T18	2		T19	7
auto[0]	len_520	105	1			T18	4		T19	2		T60	2
auto[0]	len_512	217	1			T4	2		T6	1		T21	5
auto[0]	len_504	123	1			T6	2		T19	3		T127	3
auto[0]	len_8	16	1			T142	1		T143	1		T144	1
auto[0]	len_0	4475	1			T1	3		T2	5		T3	2
auto[1]	len_2050_plus	45581	1			T1	9		T2	1		T3	2
auto[1]	len_1026_2046	3024	1			T4	26		T5	1		T16	2
auto[1]	len_514_1022	1404	1			T4	4		T17	1		T6	8
auto[1]	len_2_510	1478	1			T4	2		T18	1		T6	21
auto[1]	len_2056	115	1			T127	1		T129	1		T145	1
auto[1]	len_2048	160	1			T18	1		T6	1		T21	3
auto[1]	len_2040	100	1			T6	1		T129	2		T146	1
auto[1]	len_1032	89	1			T19	3		T56	1		T145	1
auto[1]	len_1024	1586	1			T16	1		T21	2		T19	4
auto[1]	len_1016	86	1			T18	4		T6	1		T19	4
auto[1]	len_520	73	1			T18	3		T19	1		T60	2
auto[1]	len_512	139	1			T6	2		T21	1		T19	1
auto[1]	len_504	72	1			T129	3		T147	2		T145	1
auto[1]	len_8	1266	1			T6	11		T21	61		T19	12
auto[1]	len_0	7094	1			T3	1		T4	39		T15	1

---

Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	0	2	100.00

Automatically Generated Cross Bins for msg_len_upper_cross

Bins

hmac_en

msg_len_upper_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

len_upper

65

1

T4

3

T5

2

T21

1

auto[1]

len_upper

42

1

T5

2

T19

2

T56

1