Group : hmac_env_pkg::hmac_env_cov::status_cg
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Group : hmac_env_pkg::hmac_env_cov::status_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv



Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 20 0 20 100.00
Crosses 192 0 192 100.00


Variables for Group hmac_env_pkg::hmac_env_cov::status_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
digest_swap 2 0 2 100.00 100 1 1 2
endian_swap 2 0 2 100.00 100 1 1 2
hmac_en 2 0 2 100.00 100 1 1 2
key_swap 2 0 2 100.00 100 1 1 2
sta_fifo_depth 8 0 8 100.00 100 1 1 0
sta_fifo_empty 2 0 2 100.00 100 1 1 2
sta_fifo_full 2 0 2 100.00 100 1 1 2


Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
fifo_empty_cross 32 0 32 100.00 100 1 1 0
fifo_full_cross 32 0 32 100.00 100 1 1 0
fifo_depth_cross 128 0 128 100.00 100 1 1 0


Summary for Variable digest_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for digest_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4517669 1 T1 4125 T2 5 T3 4
auto[1] 2776368 1 T1 3345 T2 1034 T3 3



Summary for Variable endian_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for endian_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2839487 1 T1 4203 T2 338 T3 4
auto[1] 4454550 1 T1 3267 T2 701 T3 3



Summary for Variable hmac_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hmac_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3144977 1 T1 4553 T2 1033 T3 5
auto[1] 4149060 1 T1 2917 T2 6 T3 2



Summary for Variable key_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for key_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4443515 1 T1 3420 T2 637 T3 5
auto[1] 2850522 1 T1 4050 T2 402 T3 2



Summary for Variable sta_fifo_depth

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for sta_fifo_depth

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fifo_depth[0] 6670426 1 T1 7275 T2 1028 T3 4
fifo_depth[1] 116436 1 T1 127 T2 9 T4 45
fifo_depth[2] 88205 1 T1 45 T2 2 T4 37
fifo_depth[3] 69287 1 T1 18 T4 43 T17 6
fifo_depth[4] 62819 1 T1 4 T4 115 T5 2
fifo_depth[5] 49423 1 T1 1 T4 54 T5 1
fifo_depth[6] 39104 1 T4 107 T5 2 T17 2
fifo_depth[7] 25769 1 T4 71 T5 3 T17 1



Summary for Variable sta_fifo_empty

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sta_fifo_empty

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 623611 1 T1 195 T2 11 T3 3
auto[1] 6670426 1 T1 7275 T2 1028 T3 4



Summary for Variable sta_fifo_full

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sta_fifo_full

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 7285262 1 T1 7470 T2 1039 T3 7
auto[1] 8775 1 T4 603 T6 99 T7 1



Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for fifo_empty_cross

Bins
sta_fifo_emptyhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 29740 1 T1 15 T3 2 T4 945
auto[0] auto[0] auto[0] auto[0] auto[1] 18631 1 T5 1 T6 1278 T21 67
auto[0] auto[0] auto[0] auto[1] auto[0] 24362 1 T1 10 T2 11 T4 632
auto[0] auto[0] auto[0] auto[1] auto[1] 21460 1 T1 41 T4 264 T5 1
auto[0] auto[0] auto[1] auto[0] auto[0] 140828 1 T6 351 T21 103 T19 355
auto[0] auto[0] auto[1] auto[0] auto[1] 30431 1 T1 21 T4 259 T17 8
auto[0] auto[0] auto[1] auto[1] auto[0] 24321 1 T4 897 T5 2 T18 1
auto[0] auto[0] auto[1] auto[1] auto[1] 26808 1 T1 18 T4 742 T17 11
auto[0] auto[1] auto[0] auto[0] auto[0] 31020 1 T6 236 T21 117 T19 1441
auto[0] auto[1] auto[0] auto[0] auto[1] 37554 1 T6 2386 T21 144 T19 274
auto[0] auto[1] auto[0] auto[1] auto[0] 34040 1 T5 1 T6 314 T21 30
auto[0] auto[1] auto[0] auto[1] auto[1] 43775 1 T1 50 T4 631 T5 1
auto[0] auto[1] auto[1] auto[0] auto[0] 50173 1 T4 2785 T18 1 T6 1145
auto[0] auto[1] auto[1] auto[0] auto[1] 44850 1 T1 23 T3 1 T5 1
auto[0] auto[1] auto[1] auto[1] auto[0] 33085 1 T1 17 T5 1 T17 12
auto[0] auto[1] auto[1] auto[1] auto[1] 32533 1 T4 252 T16 5 T6 713
auto[1] auto[0] auto[0] auto[0] auto[0] 149752 1 T1 1311 T4 62 T5 1
auto[1] auto[0] auto[0] auto[0] auto[1] 156494 1 T1 21 T5 1 T17 48
auto[1] auto[0] auto[0] auto[1] auto[0] 180992 1 T1 317 T2 325 T3 1
auto[1] auto[0] auto[0] auto[1] auto[1] 165406 1 T1 835 T4 213 T5 2
auto[1] auto[0] auto[1] auto[0] auto[0] 1709947 1 T1 239 T2 1 T5 3
auto[1] auto[0] auto[1] auto[0] auto[1] 151358 1 T1 838 T3 1 T4 383
auto[1] auto[0] auto[1] auto[1] auto[0] 161125 1 T1 82 T2 297 T3 1
auto[1] auto[0] auto[1] auto[1] auto[1] 153322 1 T1 805 T2 399 T4 297
auto[1] auto[1] auto[0] auto[0] auto[0] 464903 1 T1 491 T2 1 T4 224
auto[1] auto[1] auto[0] auto[0] auto[1] 534789 1 T1 212 T4 171 T5 2
auto[1] auto[1] auto[0] auto[1] auto[0] 447564 1 T1 222 T3 1 T4 40
auto[1] auto[1] auto[0] auto[1] auto[1] 499005 1 T1 678 T2 1 T4 11
auto[1] auto[1] auto[1] auto[0] auto[0] 505871 1 T1 446 T2 2 T4 85
auto[1] auto[1] auto[1] auto[0] auto[1] 461328 1 T1 508 T2 1 T15 750
auto[1] auto[1] auto[1] auto[1] auto[0] 455792 1 T1 270 T5 1 T16 12
auto[1] auto[1] auto[1] auto[1] auto[1] 472778 1 T2 1 T4 628 T5 5



Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for fifo_full_cross

Bins
sta_fifo_fullhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 179005 1 T1 1326 T3 2 T4 1006
auto[0] auto[0] auto[0] auto[0] auto[1] 174138 1 T1 21 T5 2 T17 48
auto[0] auto[0] auto[0] auto[1] auto[0] 203494 1 T1 327 T2 336 T3 1
auto[0] auto[0] auto[0] auto[1] auto[1] 186288 1 T1 876 T4 476 T5 3
auto[0] auto[0] auto[1] auto[0] auto[0] 1850727 1 T1 239 T2 1 T5 3
auto[0] auto[0] auto[1] auto[0] auto[1] 181342 1 T1 859 T3 1 T4 633
auto[0] auto[0] auto[1] auto[1] auto[0] 184785 1 T1 82 T2 297 T3 1
auto[0] auto[0] auto[1] auto[1] auto[1] 178584 1 T1 823 T2 399 T4 1039
auto[0] auto[1] auto[0] auto[0] auto[0] 495715 1 T1 491 T2 1 T4 224
auto[0] auto[1] auto[0] auto[0] auto[1] 572189 1 T1 212 T4 171 T5 2
auto[0] auto[1] auto[0] auto[1] auto[0] 481367 1 T1 222 T3 1 T4 40
auto[0] auto[1] auto[0] auto[1] auto[1] 542019 1 T1 728 T2 1 T4 641
auto[0] auto[1] auto[1] auto[0] auto[0] 555745 1 T1 446 T2 2 T4 2729
auto[0] auto[1] auto[1] auto[0] auto[1] 506042 1 T1 531 T2 1 T3 1
auto[0] auto[1] auto[1] auto[1] auto[0] 488607 1 T1 287 T5 2 T16 12
auto[0] auto[1] auto[1] auto[1] auto[1] 505215 1 T2 1 T4 877 T5 5
auto[1] auto[0] auto[0] auto[0] auto[0] 487 1 T4 1 T6 2 T149 21
auto[1] auto[0] auto[0] auto[0] auto[1] 987 1 T6 3 T141 1 T150 3
auto[1] auto[0] auto[0] auto[1] auto[0] 1860 1 T4 26 T6 16 T149 496
auto[1] auto[0] auto[0] auto[1] auto[1] 578 1 T4 1 T6 39 T7 1
auto[1] auto[0] auto[1] auto[0] auto[0] 48 1 T6 1 T151 46 T150 1
auto[1] auto[0] auto[1] auto[0] auto[1] 447 1 T4 9 T149 123 T141 60
auto[1] auto[0] auto[1] auto[1] auto[0] 661 1 T4 421 T6 9 T151 1
auto[1] auto[0] auto[1] auto[1] auto[1] 1546 1 T151 22 T152 22 T153 345
auto[1] auto[1] auto[0] auto[0] auto[0] 208 1 T151 76 T54 26 T152 4
auto[1] auto[1] auto[0] auto[0] auto[1] 154 1 T6 13 T154 52 T153 33
auto[1] auto[1] auto[0] auto[1] auto[0] 237 1 T6 4 T151 23 T155 5
auto[1] auto[1] auto[0] auto[1] auto[1] 761 1 T4 1 T151 74 T153 17
auto[1] auto[1] auto[1] auto[0] auto[0] 299 1 T4 141 T151 94 T152 25
auto[1] auto[1] auto[1] auto[0] auto[1] 136 1 T6 12 T141 4 T151 1
auto[1] auto[1] auto[1] auto[1] auto[0] 270 1 T151 1 T54 153 T153 1
auto[1] auto[1] auto[1] auto[1] auto[1] 96 1 T4 3 T153 84 T156 8



Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 128 0 128 100.00


Automatically Generated Cross Bins for fifo_depth_cross

Bins
sta_fifo_depthhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fifo_depth[0] auto[0] auto[0] auto[0] auto[0] 149752 1 T1 1311 T4 62 T5 1
fifo_depth[0] auto[0] auto[0] auto[0] auto[1] 156494 1 T1 21 T5 1 T17 48
fifo_depth[0] auto[0] auto[0] auto[1] auto[0] 180992 1 T1 317 T2 325 T3 1
fifo_depth[0] auto[0] auto[0] auto[1] auto[1] 165406 1 T1 835 T4 213 T5 2
fifo_depth[0] auto[0] auto[1] auto[0] auto[0] 1709947 1 T1 239 T2 1 T5 3
fifo_depth[0] auto[0] auto[1] auto[0] auto[1] 151358 1 T1 838 T3 1 T4 383
fifo_depth[0] auto[0] auto[1] auto[1] auto[0] 161125 1 T1 82 T2 297 T3 1
fifo_depth[0] auto[0] auto[1] auto[1] auto[1] 153322 1 T1 805 T2 399 T4 297
fifo_depth[0] auto[1] auto[0] auto[0] auto[0] 464903 1 T1 491 T2 1 T4 224
fifo_depth[0] auto[1] auto[0] auto[0] auto[1] 534789 1 T1 212 T4 171 T5 2
fifo_depth[0] auto[1] auto[0] auto[1] auto[0] 447564 1 T1 222 T3 1 T4 40
fifo_depth[0] auto[1] auto[0] auto[1] auto[1] 499005 1 T1 678 T2 1 T4 11
fifo_depth[0] auto[1] auto[1] auto[0] auto[0] 505871 1 T1 446 T2 2 T4 85
fifo_depth[0] auto[1] auto[1] auto[0] auto[1] 461328 1 T1 508 T2 1 T15 750
fifo_depth[0] auto[1] auto[1] auto[1] auto[0] 455792 1 T1 270 T5 1 T16 12
fifo_depth[0] auto[1] auto[1] auto[1] auto[1] 472778 1 T2 1 T4 628 T5 5
fifo_depth[1] auto[0] auto[0] auto[0] auto[0] 3145 1 T1 9 T4 21 T6 34
fifo_depth[1] auto[0] auto[0] auto[0] auto[1] 2537 1 T6 61 T21 9 T19 21
fifo_depth[1] auto[0] auto[0] auto[1] auto[0] 3530 1 T1 7 T2 9 T4 1
fifo_depth[1] auto[0] auto[0] auto[1] auto[1] 3151 1 T1 25 T4 3 T6 28
fifo_depth[1] auto[0] auto[1] auto[0] auto[0] 42506 1 T6 19 T21 18 T19 88
fifo_depth[1] auto[0] auto[1] auto[0] auto[1] 2928 1 T1 14 T17 1 T6 2
fifo_depth[1] auto[0] auto[1] auto[1] auto[0] 2995 1 T18 1 T6 12 T21 38
fifo_depth[1] auto[0] auto[1] auto[1] auto[1] 3179 1 T1 11 T4 20 T17 1
fifo_depth[1] auto[1] auto[0] auto[0] auto[0] 5861 1 T6 3 T21 23 T19 234
fifo_depth[1] auto[1] auto[0] auto[0] auto[1] 6578 1 T6 234 T21 24 T19 42
fifo_depth[1] auto[1] auto[0] auto[1] auto[0] 5370 1 T5 1 T6 1 T21 3
fifo_depth[1] auto[1] auto[0] auto[1] auto[1] 6829 1 T1 34 T6 66 T21 40
fifo_depth[1] auto[1] auto[1] auto[0] auto[0] 8631 1 T18 1 T6 181 T21 9
fifo_depth[1] auto[1] auto[1] auto[0] auto[1] 7495 1 T1 16 T15 13 T6 190
fifo_depth[1] auto[1] auto[1] auto[1] auto[0] 5606 1 T1 11 T18 1 T19 184
fifo_depth[1] auto[1] auto[1] auto[1] auto[1] 6095 1 T16 2 T6 85 T21 1
fifo_depth[2] auto[0] auto[0] auto[0] auto[0] 2599 1 T1 2 T4 3 T6 49
fifo_depth[2] auto[0] auto[0] auto[0] auto[1] 1950 1 T6 62 T21 16 T19 29
fifo_depth[2] auto[0] auto[0] auto[1] auto[0] 2501 1 T1 2 T2 2 T4 2
fifo_depth[2] auto[0] auto[0] auto[1] auto[1] 2550 1 T1 13 T4 3 T6 31
fifo_depth[2] auto[0] auto[1] auto[0] auto[0] 28794 1 T6 14 T21 20 T19 67
fifo_depth[2] auto[0] auto[1] auto[0] auto[1] 2234 1 T1 5 T17 2 T21 11
fifo_depth[2] auto[0] auto[1] auto[1] auto[0] 2375 1 T6 16 T21 40 T19 89
fifo_depth[2] auto[0] auto[1] auto[1] auto[1] 2516 1 T1 5 T4 20 T17 1
fifo_depth[2] auto[1] auto[0] auto[0] auto[0] 4626 1 T6 9 T21 26 T19 217
fifo_depth[2] auto[1] auto[0] auto[0] auto[1] 5206 1 T6 223 T21 23 T19 40
fifo_depth[2] auto[1] auto[0] auto[1] auto[0] 4302 1 T6 3 T21 2 T19 63
fifo_depth[2] auto[1] auto[0] auto[1] auto[1] 5584 1 T1 12 T4 3 T6 73
fifo_depth[2] auto[1] auto[1] auto[0] auto[0] 7060 1 T4 4 T6 205 T21 14
fifo_depth[2] auto[1] auto[1] auto[0] auto[1] 6229 1 T1 3 T15 2 T6 183
fifo_depth[2] auto[1] auto[1] auto[1] auto[0] 4551 1 T1 3 T17 1 T21 4
fifo_depth[2] auto[1] auto[1] auto[1] auto[1] 5128 1 T4 2 T16 2 T6 107
fifo_depth[3] auto[0] auto[0] auto[0] auto[0] 1950 1 T1 4 T4 17 T6 40
fifo_depth[3] auto[0] auto[0] auto[0] auto[1] 1369 1 T6 63 T21 7 T19 33
fifo_depth[3] auto[0] auto[0] auto[1] auto[0] 1773 1 T4 2 T17 5 T21 4
fifo_depth[3] auto[0] auto[0] auto[1] auto[1] 1666 1 T1 3 T4 3 T6 21
fifo_depth[3] auto[0] auto[1] auto[0] auto[0] 21750 1 T6 14 T21 11 T19 86
fifo_depth[3] auto[0] auto[1] auto[0] auto[1] 1630 1 T1 1 T6 2 T21 7
fifo_depth[3] auto[0] auto[1] auto[1] auto[0] 1650 1 T6 23 T21 8 T19 59
fifo_depth[3] auto[0] auto[1] auto[1] auto[1] 1881 1 T1 1 T4 21 T6 10
fifo_depth[3] auto[1] auto[0] auto[0] auto[0] 3721 1 T6 6 T21 15 T19 210
fifo_depth[3] auto[1] auto[0] auto[0] auto[1] 4472 1 T6 226 T21 20 T19 42
fifo_depth[3] auto[1] auto[0] auto[1] auto[0] 3732 1 T6 7 T19 74 T58 24
fifo_depth[3] auto[1] auto[0] auto[1] auto[1] 4760 1 T1 4 T6 74 T21 6
fifo_depth[3] auto[1] auto[1] auto[0] auto[0] 5801 1 T6 170 T21 6 T19 200
fifo_depth[3] auto[1] auto[1] auto[0] auto[1] 5301 1 T1 3 T6 184 T21 2
fifo_depth[3] auto[1] auto[1] auto[1] auto[0] 3760 1 T1 2 T17 1 T21 2
fifo_depth[3] auto[1] auto[1] auto[1] auto[1] 4071 1 T6 108 T19 139 T58 8
fifo_depth[4] auto[0] auto[0] auto[0] auto[0] 2150 1 T4 37 T6 41 T21 15
fifo_depth[4] auto[0] auto[0] auto[0] auto[1] 1546 1 T6 55 T21 25 T19 24
fifo_depth[4] auto[0] auto[0] auto[1] auto[0] 1966 1 T4 2 T17 3 T6 12
fifo_depth[4] auto[0] auto[0] auto[1] auto[1] 1581 1 T4 6 T5 1 T6 25
fifo_depth[4] auto[0] auto[1] auto[0] auto[0] 16111 1 T6 15 T21 18 T19 42
fifo_depth[4] auto[0] auto[1] auto[0] auto[1] 1758 1 T1 1 T4 10 T17 4
fifo_depth[4] auto[0] auto[1] auto[1] auto[0] 1835 1 T4 7 T6 19 T21 16
fifo_depth[4] auto[0] auto[1] auto[1] auto[1] 1938 1 T1 1 T4 43 T17 7
fifo_depth[4] auto[1] auto[0] auto[0] auto[0] 3487 1 T6 3 T21 15 T19 231
fifo_depth[4] auto[1] auto[0] auto[0] auto[1] 4252 1 T6 205 T21 24 T19 31
fifo_depth[4] auto[1] auto[0] auto[1] auto[0] 3557 1 T6 5 T21 15 T19 44
fifo_depth[4] auto[1] auto[0] auto[1] auto[1] 4344 1 T6 59 T21 15 T19 200
fifo_depth[4] auto[1] auto[1] auto[0] auto[0] 5564 1 T4 6 T6 188 T21 37
fifo_depth[4] auto[1] auto[1] auto[0] auto[1] 5085 1 T1 1 T5 1 T6 175
fifo_depth[4] auto[1] auto[1] auto[1] auto[0] 3584 1 T1 1 T17 6 T6 2
fifo_depth[4] auto[1] auto[1] auto[1] auto[1] 4061 1 T4 4 T16 1 T6 102
fifo_depth[5] auto[0] auto[0] auto[0] auto[0] 1514 1 T4 16 T6 32 T21 1
fifo_depth[5] auto[0] auto[0] auto[0] auto[1] 1033 1 T6 61 T21 3 T19 24
fifo_depth[5] auto[0] auto[0] auto[1] auto[0] 1332 1 T1 1 T4 4 T5 1
fifo_depth[5] auto[0] auto[0] auto[1] auto[1] 1091 1 T4 1 T6 17 T21 1
fifo_depth[5] auto[0] auto[1] auto[0] auto[0] 11945 1 T6 11 T21 7 T19 34
fifo_depth[5] auto[0] auto[1] auto[0] auto[1] 1102 1 T4 1 T6 3 T21 6
fifo_depth[5] auto[0] auto[1] auto[1] auto[0] 1273 1 T4 2 T6 24 T21 1
fifo_depth[5] auto[0] auto[1] auto[1] auto[1] 1410 1 T4 26 T6 14 T21 1
fifo_depth[5] auto[1] auto[0] auto[0] auto[0] 2941 1 T6 8 T21 13 T19 180
fifo_depth[5] auto[1] auto[0] auto[0] auto[1] 3758 1 T6 192 T21 11 T19 42
fifo_depth[5] auto[1] auto[0] auto[1] auto[0] 2985 1 T6 5 T21 3 T19 32
fifo_depth[5] auto[1] auto[0] auto[1] auto[1] 3816 1 T4 1 T6 54 T21 5
fifo_depth[5] auto[1] auto[1] auto[0] auto[0] 4395 1 T4 2 T6 161 T21 8
fifo_depth[5] auto[1] auto[1] auto[0] auto[1] 4458 1 T6 145 T19 151 T128 29
fifo_depth[5] auto[1] auto[1] auto[1] auto[0] 3036 1 T21 3 T19 154 T56 55
fifo_depth[5] auto[1] auto[1] auto[1] auto[1] 3334 1 T4 1 T6 109 T19 125
fifo_depth[6] auto[0] auto[0] auto[0] auto[0] 1288 1 T4 35 T6 25 T21 7
fifo_depth[6] auto[0] auto[0] auto[0] auto[1] 1039 1 T5 1 T6 113 T21 5
fifo_depth[6] auto[0] auto[0] auto[1] auto[0] 1139 1 T4 2 T17 1 T6 4
fifo_depth[6] auto[0] auto[0] auto[1] auto[1] 876 1 T4 4 T6 16 T21 3
fifo_depth[6] auto[0] auto[1] auto[0] auto[0] 8163 1 T6 13 T21 10 T19 18
fifo_depth[6] auto[0] auto[1] auto[0] auto[1] 1002 1 T4 1 T6 2 T21 4
fifo_depth[6] auto[0] auto[1] auto[1] auto[0] 1159 1 T4 1 T5 1 T6 32
fifo_depth[6] auto[0] auto[1] auto[1] auto[1] 1108 1 T4 58 T6 8 T21 16
fifo_depth[6] auto[1] auto[0] auto[0] auto[0] 2355 1 T6 4 T21 6 T19 160
fifo_depth[6] auto[1] auto[0] auto[0] auto[1] 2927 1 T6 164 T21 6 T19 30
fifo_depth[6] auto[1] auto[0] auto[1] auto[0] 2335 1 T6 3 T21 1 T19 16
fifo_depth[6] auto[1] auto[0] auto[1] auto[1] 3122 1 T6 52 T21 12 T19 141
fifo_depth[6] auto[1] auto[1] auto[0] auto[0] 3616 1 T4 4 T6 104 T21 15
fifo_depth[6] auto[1] auto[1] auto[0] auto[1] 3485 1 T6 121 T21 5 T19 133
fifo_depth[6] auto[1] auto[1] auto[1] auto[0] 2529 1 T17 1 T21 1 T19 105
fifo_depth[6] auto[1] auto[1] auto[1] auto[1] 2961 1 T4 2 T6 78 T21 1
fifo_depth[7] auto[0] auto[0] auto[0] auto[0] 854 1 T4 17 T5 2 T6 16
fifo_depth[7] auto[0] auto[0] auto[0] auto[1] 695 1 T6 91 T21 1 T19 6
fifo_depth[7] auto[0] auto[0] auto[1] auto[0] 727 1 T21 2 T19 3 T58 1
fifo_depth[7] auto[0] auto[0] auto[1] auto[1] 584 1 T4 1 T6 15 T21 3
fifo_depth[7] auto[0] auto[1] auto[0] auto[0] 4986 1 T6 7 T21 7 T19 11
fifo_depth[7] auto[0] auto[1] auto[0] auto[1] 797 1 T6 3 T21 4 T19 4
fifo_depth[7] auto[0] auto[1] auto[1] auto[0] 754 1 T5 1 T6 29 T19 20
fifo_depth[7] auto[0] auto[1] auto[1] auto[1] 747 1 T4 51 T17 1 T6 10
fifo_depth[7] auto[1] auto[0] auto[0] auto[0] 1638 1 T6 5 T21 7 T19 110
fifo_depth[7] auto[1] auto[0] auto[0] auto[1] 2013 1 T6 110 T21 8 T19 20
fifo_depth[7] auto[1] auto[0] auto[1] auto[0] 1613 1 T6 5 T19 5 T58 8
fifo_depth[7] auto[1] auto[0] auto[1] auto[1] 2169 1 T4 1 T6 30 T21 2
fifo_depth[7] auto[1] auto[1] auto[0] auto[0] 2410 1 T4 1 T6 73 T19 73
fifo_depth[7] auto[1] auto[1] auto[0] auto[1] 2236 1 T6 65 T19 100 T128 8
fifo_depth[7] auto[1] auto[1] auto[1] auto[0] 1691 1 T19 77 T56 35 T129 61
fifo_depth[7] auto[1] auto[1] auto[1] auto[1] 1855 1 T6 57 T21 2 T19 75

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