Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	17942950	1			T1	15032		T2	4569		T3	1664
all_pins[1]	17942950	1			T1	15032		T2	4569		T3	1664
all_pins[2]	17942950	1			T1	15032		T2	4569		T3	1664

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	45861224	1			T1	39587		T2	10736		T3	4646
values[0x1]	7967626	1			T1	5509		T2	2971		T3	346
transitions[0x0=>0x1]	7967462	1			T1	5509		T2	2971		T3	346
transitions[0x1=>0x0]	7967475	1			T1	5509		T2	2971		T3	346

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	17922627	1			T1	15013		T2	4566		T3	1658
all_pins[0]	values[0x1]	20323	1			T1	19		T2	3		T3	6
all_pins[0]	transitions[0x0=>0x1]	20244	1			T1	19		T2	3		T3	6
all_pins[0]	transitions[0x1=>0x0]	7946965	1			T1	5490		T2	2968		T3	340
all_pins[1]	values[0x0]	17942678	1			T1	15032		T2	4569		T3	1664
all_pins[1]	values[0x1]	272	1			T4	3		T6	5		T21	4
all_pins[1]	transitions[0x0=>0x1]	233	1			T4	3		T6	5		T21	3
all_pins[1]	transitions[0x1=>0x0]	20284	1			T1	19		T2	3		T3	6
all_pins[2]	values[0x0]	9995919	1			T1	9542		T2	1601		T3	1324
all_pins[2]	values[0x1]	7947031	1			T1	5490		T2	2968		T3	340
all_pins[2]	transitions[0x0=>0x1]	7946985	1			T1	5490		T2	2968		T3	340
all_pins[2]	transitions[0x1=>0x0]	226	1			T4	3		T6	5		T21	3